What are the responsibilities and job description for the Hardware Architect position at Acceler8 Talent?
Hardware Architect
Acceler8 Talent is seeking an experienced Hardware Architect to join a well funded startup whose hardware promises to drastically change the economics of compute for the worlds' largest models.
With over $600m raised, and a world-class team with a track record of shipping highly successful products, this company abandons legacy chip design assumptions and strives for the best possible solution for every aspect of their chip - there is no such thing as "good enough".
As a Hardware Architect, you will define the ISA and microarchitecture for next-generation compute engines, working at the intersection of research, software, and hardware. You will translate ML/AI workload requirements into architectural specifications and guide the design from concept through first silicon and bring-up.
What You’ll Do Here
- Define ISA and microarchitecture for compute cores, memory subsystems, and interconnects
- Derive architectural requirements directly from ML/AI use cases and emerging model trends
- Author detailed architectural specifications and structured interface definitions
- Specify numeric formats and quantization strategies optimized for AI workloads
- Estimate area, timing, and power to inform architectural tradeoffs
- Collaborate closely with Research, Software, RTL, and Physical Design teams to ensure cohesive execution
- Participate in architecture reviews, design reviews, and test planning
- Support first-silicon bring-up and post-silicon debug
Who You Are
- Strong background in computer architecture with deep understanding of modern compute systems
- 3 years experience translating workloads/algorithms into hardware architectures
- Proven ability to evaluate hardware cost, area, timing, and power tradeoffs
- Excellent fundamentals in latency, throughput, and scalability theory
- Knowledge of numeric formats, quantization techniques, and precision tradeoffs for ML workloads
- Experience with programming and performance/code optimization
- Ability to define structured interfaces and bit-level encodings using constructs such as structs and tagged unions
- Strong verbal and written communication skills, with the ability to clearly document and defend architectural decisions
- Comfortable working cross-functionally in a fast-paced, execution-driven environment
Bonus Points If You Have
- Familiarity with parallel execution models such as VLIW, SIMD, or vector architectures
- Experience designing custom ML silicon or AI systems
If you're excited about defining the architecture behind the next generation of AI compute, apply here or reach out to me at ltomaszko@acceler8talent.com to discuss further.
Salary : $300,000 - $500,000