Mixed Signal Verification Engineer

Job Title: Mixed Signal Verification Engineer

Experience: 5 to 8 years

Location: USA - Austin

Employment Type: Full-time

Visa Sponsorship: H1-B Sponsorship Available

Job Description

About The Position

We are seeking a Mixed-Signal Verification Engineerto support the verification of high-speed communication designs that integrate complex digital and analog components. This role focuses on building and validating verification environments that bridge digital verification methodologies with analog design behavior. This is a hands-on role working closely with analog designers, digital designers, and verification engineers to ensure correctness and performance across unit-, subsystem-, and full-chip simulations. Location: Austin, TX Work Model: On-site, five days per week (required)

Requirements Key Responsibilities

• Develop and execute verification strategies for mixed-signal designs using UVM-based methodologies
• Create and maintain behavioral models for analog blocks in collaboration with analog design teams
• Write, run, and debug SystemVerilog / UVM testbenches for mixed-signal blocks
• Validate behavioral models through simulation and debug across multiple abstraction levels
• Perform and troubleshoot unit-level, subsystem-level, and top-level mixed-signal simulations
• Analyze simulation results, identify root causes, and collaborate with design teams to resolve issues
• Contribute to test plans, verification documentation, and continuous improvement of verification flows
  
  

Minimum Qualifications

• 2 years of experience in mixed-signal verification, behavioral modeling, or closely related verification roles
• Strong experience with UVM-based verification methodologies
• Proficiency in Verilog / SystemVerilog
• Experience working with mixed-signal designs using digital verification tools
• Working knowledge of analog design concepts sufficient to model and verify analog behavior
• Ability to debug complex verification environments and communicate findings clearly
  
  

Preferred Qualifications

• Experience using Cadence Virtuoso schematic and simulation environments
• Familiarity with both Cadence and Synopsys toolchains
• Experience developing scalable and reusable verification environments and testbenches
• Exposure to high-speed or high-performance communication designs
• Experience with waveform debug tools (e.g., Verdi)
• Strong collaboration skills in cross-functional engineering team
  
  

Compensation Base Salary: USD 160,000 - $180,000 Meaningful Equity Other

• Will sponsor H1-B
• On-site in Austin, TX, five days a week is a MUST
• Full Medical, Dental & Vision Benefits
  
  

Must Have

Must have current recent experience as a Signal Verification Engineer.

Job stability is mandatory - no job hoppers accepted

Candidates with breaks will not be accepted

• 2 years of experience in mixed-signal verification, behavioral modeling, or closely related
  
  

verification roles

• Strong experience with UVM-based verification methodologies
• Proficiency in Verilog / SystemVerilog
• Experience working with mixed-signal designs using digital verification tools
• Working knowledge of analog design concepts sufficient to model and verify analog behavior
• Ability to debug complex verification environments and communicate findings clearly
  
  

On-site in Austin, TX, five days a week.

Nice to Haves

• Experience using Cadence Virtuoso schematic and simulation environments
• Familiarity with both Cadence and Synopsys toolchains
• Experience developing scalable and reusable verification environments and testbenches
• Exposure to high-speed or high-performance communication designs
• Experience with waveform debug tools (e.g., Verdi)
• Strong collaboration skills in cross-functional engineering team
• Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative
  
  

team environment.

• Communication: Strong communication skills, including the ability to write test plans, present
  
  

results, and communicate clearly with multi-functional teams