What are the responsibilities and job description for the Digital Design Engineer position at Xcelerium?
About Xcelerium:
Xcelerium is a fabless semiconductor company established in 2020 by experienced team from Qualcomm, Intel and Broadcom. Xcelerium develops silicon and software for sensor processing, communications and latency-sensitive AI applications. Working at Xcelerium will provide an opportunity to work on a complex development from the ground up and become familiar with cutting edge technologies such as RISC-V, digital signal processing, machine learning, many-core parallel processing using CUDA/OpenCL, inner workings of frameworks such as TensorFlow, PyTorch, OpenGL, real-time operating systems and embedded In addition, the application domains will be 5G, UAVs/Drone, Robots, and Autonomous Vehicles which provide enormous scope for growth and making an impact.
Job Summary:
As an ASIC RTL Design Engineer, you will work on developing and implementing cutting-edge complex digital designs, SoCs, and industry-leading RISC-V cores. You will collaborate with the RTL design team, firmware team, and physical implementation team to optimize the design for performance, power efficiency, and area.
Key Responsibilities
- Architect, design, and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.
Technical Qualifications
- Bachelor’s in Computer Engineering or Electrical Engineering from a reputable institution
- 5 years of relevant professional experience
- Excellent understanding of logic design using hardware description languages like Verilog/SystemVerilog is required.
- Familiarity with processor architecture, memory and cache subsystems, on-chip interconnects and network-on-chip technology
- Familiarity with either UVM based verification flow
- Familiarity with RTL to GDS design flow is required
- Knowledge of RISC-V architectures is a strong plus
- Strong programming skills in Python, C/C , Chisel or assembly language is highly desirable
- Experience with fixed point arithmetic and data path design is desirable
Other Requirements
- Passion for learning new technologies
- Taking pride in always producing high quality code and documentation
- Excellent communication skills
- Comfortable and willing to work with team members from different disciplines, different levels and across time-zones
Location: on-site in Irvine, CA
Alternate locations: Santa Clara, CA; San Diego, CA
Job Type: Full-time
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Life insurance
- Paid time off
- Vision insurance