What are the responsibilities and job description for the Test Development Engineer position at WorkPlace?
Job Title: DFT Engineer (Design for Test) – Semiconductor
Location: Austin, TX (On-site)
Experience: 10–15 Years
We are looking for an experienced DFT Engineer to drive end-to-end Design-for-Test (DFT) architecture and implementation for complex digital and mixed-signal SoCs. This role involves close collaboration with design, verification, and backend teams to ensure high-quality, testable silicon.
Key Responsibilities- Define and implement SoC-level DFT architecture (ATPG, Scan, MBIST, LBIST)
- Insert and integrate DFT structures: scan chains, boundary scan, compression, TAP, clock control, etc.
- Execute hierarchical DFT design and integration
- Debug DFT DRC issues and improve test coverage/quality
- Develop and validate silicon test strategies (post-silicon bring-up, ATE debug)
- Work on MBIST implementation and memory test integration
- Support test planning for analog/mixed-signal IPs
- Document DFT methodologies and processes
- Strong experience in DFT architecture, insertion, and validation
- Hands-on experience with silicon bring-up, ATE debug, ATPG (including compressed patterns), MBIST, and JTAG
- Solid understanding of fault modeling and test coverage
- Experience in IP integration (memories, TAP controllers, MBIST, test controllers)
- Proficiency in EDA tools such as DFT Compiler/Fusion Compiler, Tessent, Modus, SpyGlass, TestKompress
- Strong understanding of ASIC design flow (synthesis, simulation, verification)
- Must have recent hands-on experience in DFT
- Strong stability in career (no frequent job changes or gaps)
- Willingness to work on-site in Austin, TX (5 days/week)