Demo

Principal Verification Engineer

West Valley Staffing Group
San Jose, CA Full Time
POSTED ON 10/23/2025 CLOSED ON 12/22/2025

What are the responsibilities and job description for the Principal Verification Engineer position at West Valley Staffing Group?

Principal Verification Engineer

Overview

Our client, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Verification Engineer to join our Memory Interconnect Design team.  You will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

 Are you a seasoned Verification Engineer ready to make a real impact?
Join our client in this high-visibility role where you’ll lead the charge in defining and executing Verification Strategies across multiple product lines and global sites. This is your chance to take full ownership, collaborate with top-tier design teams, and shape the future of cutting-edge technology.

 Enjoy the best of both worlds with our hybrid role, working alongside top talent in cutting-edge facilities while enjoying the vibrant lifestyle each city offers!

Whether it’s the innovation and energy of Silicon Valley (San Jose, CA) or near the Santa Monica mountains in scenic Agoura Hills, CA.

You can also be in the thriving Tech Suburb in Johns Creek, GA just outside of Atlanta to the renowned Research Triangle Park in Morrisville, North Carolina.

 Responsibilities                                                                                               

 How You’ll Make a Difference

As our Technical Verification Lead, you’ll be at the heart of our chip development process—ensuring our designs are robust, reliable, and ready for the real world. Your leadership and technical expertise will directly shape the success of our silicon products.

 Here’s how you’ll contribute

  • Lead the charge on full-chip and block-level verification, ensuring our designs meet the highest standards.
  • Collaborate closely with Architects, Logic, and Mixed-Signal Designers to define and execute robust verification plans.
  • Build advanced test environments using UVM methodology, including  test benches, monitors, and scoreboards.
  • Drive quality by achieving code coverage goals and delivering thoroughly verified silicon.
  • Partner with Lab/System teams to develop test plans, support silicon bring-up, and debug real-world issues.
  • Innovate within a dynamic R&D environment, contributing to the evolution of our verification flows and methodologies.
  • Mentor and inspire junior engineers, helping to grow the next generation of technical talent.

Qualifications

What Makes You a Great Fit

  • MSEE & 10 years or PhD EE & 7 years’ experience of Verification 
  • Significant Experience with coding in System Verilog or Verilog and UVM methodology 
  • Significant Experience with standard ASIC Verification flow/software tools  
    1. Simulation tools:  Synopsys VCS, Cadence Xcelium
    2. Verification Methodologies:  UVM (Universal Verification Methodology)
    3. Coverage & Analysis:  Cadence IMC (Incisive Metrics Center)
  • Strong knowledge of scripting, Linux/Unix environment 
  • Experience in leading and driving technical solutions across organization 
  • Good written & verbal communication skills
  • A strong commitment & ability to work in cross functional and globally dispersed teams 

 What Makes You Shine

  • Verification of DDR memory interfaces
  • Experience working in Analog/Mixed-Signal Products
  • Verification Methodologies:  SVA (System/Verilog Assertions)
  • Regression Management:  Jenkins (CI/CD Integration)

About Our Client:

With 30 years of innovation and semiconductor expertise, our client leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. 

 Our client offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. 

Our salary ranges are determined by role, level and location.  The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

 Our client is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts to help enhance collaboration, teamwork, engagement, and innovation. Our client believe that we can be our best when every member of our organization feels respected, included, and heard.

Salary.com Estimation for Principal Verification Engineer in San Jose, CA
$181,794 to $215,688
If your compensation planning software is too rigid to deploy winning incentive strategies, it’s time to find an adaptable solution. Compensation Planning
Enhance your organization's compensation strategy with salary data sets that HR and team managers can use to pay your staff right. Surveys & Data Sets

What is the career path for a Principal Verification Engineer?

Sign up to receive alerts about other jobs on the Principal Verification Engineer career path by checking the boxes next to the positions that interest you.
Income Estimation: 
$131,953 - $159,624
Income Estimation: 
$169,825 - $204,021
Income Estimation: 
$166,631 - $195,636
Income Estimation: 
$162,237 - $199,353
Income Estimation: 
$181,083 - $218,117
Income Estimation: 
$131,953 - $159,624
Income Estimation: 
$169,825 - $204,021
Income Estimation: 
$166,631 - $195,636
Income Estimation: 
$162,237 - $199,353
Income Estimation: 
$181,083 - $218,117
Income Estimation: 
$162,237 - $199,353
Income Estimation: 
$222,110 - $256,974
Income Estimation: 
$224,976 - $270,947
Income Estimation: 
$205,834 - $254,869
Income Estimation: 
$242,530 - $287,120
Income Estimation: 
$85,996 - $102,718
Income Estimation: 
$111,859 - $131,446
Income Estimation: 
$110,457 - $133,106
Income Estimation: 
$105,809 - $128,724
Income Estimation: 
$122,763 - $145,698
Income Estimation: 
$205,834 - $254,869
Income Estimation: 
$150,467 - $192,499
Income Estimation: 
$149,289 - $190,988
Income Estimation: 
$97,457 - $126,589
Income Estimation: 
$176,972 - $219,172
This job has expired.
Employees: Get a Salary Increase
View Core, Job Family, and Industry Job Skills and Competency Data for more than 15,000 Job Titles Skills Library

Not the job you're looking for? Here are some other Principal Verification Engineer jobs in the San Jose, CA area that may be a better fit.

  • Marvell Semiconductor, Inc. Santa Clara, CA
  • About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cl... more
  • 19 Days Ago

  • Nokia San Jose, CA
  • Job Description In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Ne... more
  • 20 Days Ago

AI Assistant is available now!

Feel free to start your new journey!