What are the responsibilities and job description for the Senior ASIC Design Engineer position at Vivid Technology?
Fresh off a successful Series B funding round, this cutting-edge startup is building chip-scale THz imaging technology that will redefine sensing at scale. They are now looking for an experienced Digital ASIC Design Engineer to help drive next-generation SoCs from architecture through silicon.
In this role, you’ll own key digital IP development while working closely with mixed-signal, RF, and systems teams to bring a transformative product to life.
Responsibilities
- Architect, design, and implement digital IP for advanced mixed-signal SoCs
- Develop high-quality RTL (SystemVerilog/Verilog) for control logic, calibration engines, digital signal pipelines, serializers/SerDes, and high-speed interfaces
- Define and model SoC-level digital architectures, data paths, and system-level integration points
- Collaborate with AMS and RF engineers on interfacing AFE, ADC/DAC, and calibration blocks
- Own or contribute to verification: UVM environments, assertions, testbenches, coverage, and AMS co-simulation
- Drive synthesis, lint, CDC/RDC, STA, and collaborate on PnR to ensure timing and power closure
- Support DFT insertion, scan, BIST, and silicon bring-up/debug
- Create specification documents, design reviews, and documentation for digital IP and SoC architecture
- Work with cross-functional teams (architecture, systems, packaging, firmware) throughout the full chip lifecycle
Skills & Experience
- Degree in EE/CE (MS/PhD preferred)
- Strong hands-on experience with digital ASIC / SoC design
- Expert RTL design skills (SystemVerilog/Verilog)
- Solid understanding of digital architecture, clocking, resets, power domains, clock-domain crossing (CDC)
- Experience with synthesis, STA, and timing/power optimization
- Familiarity with verification methodologies (UVM preferred) and mixed-signal simulation flows
- Ability to collaborate in mixed-signal environments and work with analog/RF teams
- Experience with silicon bring-up, debug, and lab validation
📩 Interested?
Connect, DM me or send your resume to: ben.h@vividtechnology.io