ASIC/FPGA Research Engineer - Digital Design

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA.

Perform digital hardware design in a fast-moving research setting and work toward a better and more secure future. ISI’s CS&T Division has an opening in Arlington, VA for an ASIC/FPGA Research Engineer – Digital Design, to perform front-end digital design of advanced ASIC or FPGA-based prototypes addressing problems of national importance. The Engineer will work on a cutting-edge team to develop novel computer architectures, RTL models, and systems-on-chip, and will demonstrate system prototypes. Gain experience working with top research sponsors such as DARPA, IARPA, and the CHIPS Act. Benefit from a collaborative, flexible university setting with rich learning and growth opportunities.

This position does not require any security clearance. The work can be performed on a hybrid schedule that includes some regular days at the Arlington, VA office.

Tasks may include:

• Support research efforts by implementing technical solutions to novel research problems
• Work closely with senior researchers and contribute to team efforts to transform ideas into implemented solutions and prototypes
• Contribute to system implementation and documentation, and to publications
• Initiate the design, development and implementation of technology research projects
• Investigate the feasibility of applying scientific principles and concepts to potential inventions and products
• Plan and execute applied research
• May oversee staff and students

Position-specific JOB QUALIFICATIONS:

• Degree in Electrical Engineering, Computer Engineering or related field
• Bachelor’s degree with >3 years of experience, or Master’s degree
• Demonstrated success creating digital designs with Verilog or VHDL
• Solid understanding of computer architecture
• Demonstrated skills with scripting, revision control, and debugging/maintaining equipment and tools

Preferred Job Qualifications:

• Experience with FPGA-based design and bring-up
• Experience with design verification
• Familiarity with agile hardware design methodologies
• Effective at verbal communication and giving clear explanations

This position is funded by a contract or grant and may be funded by a subsequent contract or grant. Accordingly, your position is contingent upon receipt of the necessary funding from this or any subsequent [contract/grant] to continue employment. In the event (a) funding for your position changes and it becomes necessary to adjust your percentage of effort; (b) or it becomes necessary for your employment with the University of Southern California to end, you will receive one (1) month written notification of termination.

According to university policy, no severance benefits are paid to employees hired under a contract or grant. When you leave, your final paycheck will include pay for days worked, and for accrued and unused vacation. The university does not pay for accrued and unused sick days upon termination.

The annual base salary range for this position is $107,196 - $140,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

Minimum Education: Bachelor's degree Minimum Experience: 5 years Minimum Skills: Knowledge of one or more relevant programming languages (e.g., Python, C , Goolang). Experience with Linux.

Salary : $107,196 - $140,000