What are the responsibilities and job description for the Sr. Asic Design Verification Engineer position at VentureSoft Global?
Job Title: Senior ASIC Design Verification Engineer
Location: Austin, TX (Onsite/Hybrid)
Experience: 15 Years
Experience: 15 Years
Job Summary
We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.
Primary Skills (Must Have)
- SystemVerilog & UVM
- Constrained Random Verification (CRV)
- Functional Coverage & Coverage Closure
- RTL Debug & ASIC/SoC Verification
Key Responsibilities
- Develop UVM/SystemVerilog verification environments.
- Create test plans, testbenches, sequences, scoreboards, and checkers.
- Perform block-level and full-chip ASIC/SoC verification.
- Execute constrained-random and directed testing.
- Debug RTL issues and drive functional coverage closure.
- Collaborate with design, architecture, and validation teams.
- Support regression, verification signoff, and tape-out activities.
Preferred Skills
- CPU/Processor or Memory Subsystem Verification
- SVA (SystemVerilog Assertions)
- ARM, RISC, AI/ML Accelerator, or GPU verification
- Experience with VCS, Questa, or Xcelium
- Python or C/C
Education
Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.