What are the responsibilities and job description for the Group Director, Design Engineering - Front End position at UXR Hunt?
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.
This is a leadership role where you will be responsible for:
Technical Leadership
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
Design & Microarchitecture
Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
RTL Development
Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
Verification & Signoff
Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
Collaboration
Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Qualifications
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
We’re doing work that matters. Help us solve what others can’t.
Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.
This is a leadership role where you will be responsible for:
Technical Leadership
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
Design & Microarchitecture
Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
RTL Development
Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
Verification & Signoff
Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
Collaboration
Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Qualifications
- 10 years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
- Proven experience in leading and managing complex engineering projects
- Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
- Expert in RTL design (Verilog), simulators debuggers
- Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
- Experience in driving results in multi-disciplinary organization
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
We’re doing work that matters. Help us solve what others can’t.