What are the responsibilities and job description for the Memory PHY RTL Design Engineer position at TPI Global Solutions?
We are seeking a skilled Memory PHY RTL Design Engineer to join our team working on advanced memory interface technologies.
Key Responsibilities:
- Design and develop RTL for high-speed memory PHY IP
- Collaborate on PHY architecture and digital design implementation
- Perform timing synthesis and clock domain crossing analysis
- Work with cross-functional teams on verification and validation
- Debug and resolve design issues at RTL and firmware levels
Required Skills:
- Strong RTL design experience with Verilog/SystemVerilog
- Knowledge of DDR/LPDDR memory interfaces
- Experience with UVM verification methodology
- Understanding of PHY-level design considerations
- Familiarity with synthesis and timing closure
Preferred Qualifications:
- Experience with memory controller designs
- Scripting skills (Python, Perl, or TCL)
- Knowledge of mixed-signal design concepts
Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
