Demo

ASIC/RTL Design Engineer

TPI Global Solutions
San Jose, CA Contractor
POSTED ON 6/2/2026
AVAILABLE BEFORE 7/1/2026

Title: ASIC/RTL Design Engineer

Location: San Jose, CA (Onsite).

Duration: 06-month contract with possible extension.

Employment Type: W2 Only (No C2C or 1099).


Job Summary:

We are seeking a highly motivated ASIC/RTL Design Engineer with 3–5 years of experience in digital hardware design and ASIC development. The ideal candidate will have hands-on experience in RTL design using Verilog/SystemVerilog, IP integration, and working across the complete ASIC design lifecycle from architecture and specification through validation. This role requires strong technical expertise, problem-solving skills, and the ability to collaborate with cross-functional design and verification teams.

Key Responsibilities:

  • Develop, implement, and maintain RTL designs using Verilog and SystemVerilog.
  • Participate in ASIC development activities from specification, design, integration, verification, and validation.
  • Perform IP integration and subsystem-level design activities.
  • Collaborate with verification engineers to ensure design quality and functionality.
  • Support hardware validation, debug, and post-IP integration activities.
  • Create and maintain design documentation, technical specifications, and engineering collateral.
  • Analyze and resolve design issues throughout the ASIC development cycle.
  • Develop scripts and automation tools to improve design, validation, and debug efficiency.
  • Work closely with architecture, verification, physical design, and validation teams to ensure successful project execution.

Required Qualifications:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 3–5 years of ASIC/RTL design experience.
  • Strong hardware design background with hands-on RTL development experience.
  • Experience working through complete ASIC design cycles from specification to validation.
  • Understanding of IP integration and subsystem-level design.
  • Knowledge of verification methodologies and post-IP validation processes.
  • Experience creating and maintaining hardware design documentation.

Required Technical Skills:

  • Verilog
  • SystemVerilog
  • RTL Design and Debug
  • ASIC Design Flow
  • IP Integration
  • Hardware Validation
  • Scripting and Automation (Python, Perl, Shell, or similar)

Hourly Wage Estimation for ASIC/RTL Design Engineer in San Jose, CA
$58.00 to $67.00
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