Senior FPGA SoC Engineer

About The Company

Our client is a well-established global technology provider delivering satellite and space communications, wireless and terrestrial networks, and public-safety systems to commercial and government customers worldwide. The organization is investing heavily in its next stage of growth and is looking for engineers who enjoy solving hard problems and shaping how things get built.

The Opportunity

You will take technical ownership of complex FPGA SoC designs for satellite communication platforms. The work covers the full design flow: integrating third-party and in-house IP, writing high-performance RTL, and developing the userspace drivers and embedded firmware that make the hardware usable. You will design, build, debug, and verify these systems end to end, working closely with teammates and engineering management.

What You'll Do

• Design, implement, document, debug, and test FPGA SoC systems, including:
• Integrating IP into FPGA projects through synthesis and implementation
• Developing high-performance FPGA IP in VHDL and SystemVerilog
• Writing userspace drivers for FPGA IP in C
• Writing firmware for embedded microcontrollers in C
• Communicate clearly and collaborate effectively with peers and engineering leadership
  
  

What You Bring

• Deep digital design skills with hands-on FPGA or ASIC SoC experience
• Strong implementation experience in Client/Altera Quartus or AMD/Xilinx Vivado
• Experience designing and debugging SoC systems built around AMBA AXI and APB interfaces
• A track record of building high-throughput, pipelined AXI-Stream IP optimized for maximum clock frequency
• Ability to build RTL simulations that catch and resolve most issues before testing on hardware
• Working knowledge of static timing analysis and SDC constraints, including reading STA reports and examining post-synthesis netlists and placement to fix failing paths
• Experience contributing to schematic capture and PCB layout for the FPGA portions of a board
• Implementation experience with at least one high-speed serial protocol, such as PCI Express, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-R4, or 100GBASE-R4
• Experience implementing network protocols across the stack:
• Layer 1: IEEE 802.3 Ethernet (1G to 100G), including Cisco and SFP/QSFP MSA standards
• Layers 2/3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
• Upper layer, strongly preferred: VITA 49.2, IEEE-ISTO 4900 (DIFI), and/or eCPRI
• Proficiency in C, C , and Git
• Proficiency with standard office and diagramming tools (Word, Excel, PowerPoint, Visio)
• Experience supporting multi-disciplinary, cross-functional, matrixed teams
  
  

Nice to Have

• Working knowledge of digital IF streaming standards such as VITA 49.2, DIFI, or eCPRI ( strongly preferred)
• Familiarity with embedded Linux: kernel, Yocto, U-Boot, and device tree
• Familiarity with satellite waveforms such as DVB-S2X and/or 5G NTN (3GPP Release 17/18)
• Understanding of network security in zero-trust environments
• Experience with partial reconfiguration (DFX) or PCIe CvP
• Active DoD clearance, or ability to obtain one
  
  

Education & Experience

• Bachelor's degree in electrical or computer engineering, or a related field
• 5 years of FPGA or ASIC SoC design experience
  
  

Notes for this one

• Technical lists are the hardest part to disguise. Protocol and tool names (AXI, VITA 49.2, Vivado, DIFI) can't be changed without misrepresenting the role, so I reordered and regrouped them and reworded the surrounding phrasing. A search on a distinctive string of these terms could still surface the original, so run a quoted-phrase test on a few lines.
• Fixed a typo carried over from the original: "40GBASE-4” is written as 40GBASE-R4 here. Please confirm with the client that this is what they meant (it may be 40GBASE-R4 or 40GBASE-KR4/CR4/SR4).
• Reporting line and team name are omitted ( "Senior Director, Engineering” and "FPGA SoC Group”) since they help identify the employer. Add a generic version back if you want it.
• Clearance and on-site requirements are kept, since they affect candidate eligibility and should not be hidden.
• The niche combination of satellite comms, DIFI/VITA 49.2, and Chandler-area on-site may still point people familiar with the industry toward the employer. That's hard to avoid without making the role vague.
  
  

Equal Opportunity Employer, including disability and protected veteran status