Staff SRAM Compiler Engineer, AI Hardware

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence throughcutting-edgehardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla's machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Teslaremainsa leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit,methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects,building onour in-house SOC designexpertise. This position entails the design,constructionand integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization.

OurAI Hardware engineeringteam designs high-performance SoCs where memory architecture directlydetermineschip PPA. As a Staff SRAM Compiler Engineer, you will own SRAM compilation, configuration, and validation - partnering with architecture teams to define banking strategies anddeliveringmemory macros that maximize density, speed, and power efficiency. Your work sets the foundation for howcomputeblocksaccessmemory across the chip.

• Compile andvalidateSRAM macros across depth, width, port, and mux configurations using industry memory compilers
• Partner with architecture teams to define banking strategies - evaluate tradeoffs between number of banks, port configurations, and access patterns to hit PPA targets
• OptimizeSRAM configurations for maximum bit-cell density and access speed - drive aspect ratio, redundancy, and compileroptionchoices
• Analyze and minimize SRAM read and write power - characterize active, leakage, and retention power across PVT corners
• Own delivery of all SRAM physical and logical views - GDS, LEF, Liberty timing models, and abstracts -validatedfor implementation and signoff
• Build andmaintainautomated SRAM compilation flows using agentic AI to generate, configure, andvalidatememory macros across design variants
• Support RTL teams on SRAM hook-up - review wrapper RTL,validateinterface timing, and resolve connectivity and protocol issues
• Drive SRAM BIST and redundancy integration -validaterepair schemes and yield enhancement strategies
• Characterize SRAM timing across MMMC corners andvalidateagainst STA signoff requirements
• Evaluate new compiler releases and bit-cell options at advanced nodes - benchmark PPA against current baselines

• Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience
• 7 years of SRAM compiler and memory design experience on high-performance SoCs
• Deepexpertisein SRAM banking, configuration, and PPA optimization
• Hands-on experience with industry memory compilers (ARM, Synopsys, Cadence, or equivalent)
• Strong understanding of SRAM read/write power, leakage, and retention characteristics
• Experience delivering complete SRAM macro views for physical implementation and signoff
• Ability to use agentic AI flows to automate SRAM compilation, configuration sweeps, and validation