What are the responsibilities and job description for the Staff Logic Design Engineer position at Teledyne LeCroy?
About Teledyne LeCroy
Teledyne LeCroy is a global leader in protocol analysis and test solutions for high-speed serial data communications. Our high-speed protocol analyzers are trusted by top-tier semiconductor and system companies to validate and debug cutting-edge technologies in data centers, AI/ML, storage, and networking.
Role Overview
We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience, team play, spirit and drive, to join a dynamic team that develops leading edge test and measurement products. Join our high-speed Protocol Team as a Staff Logic Design Engineer, where you'll architect and implement high-performance digital logic for protocol capture, analysis, and emulation. You’ll work on FPGA-based systems that decode and analyze High speed protocols (PCIe, USB, Ethernet etc.) in real time, collaborating with cross-functional teams to deliver industry-leading solutions.
Key Responsibilities
- RTL Design & Microarchitecture
- Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management.
- Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource efficiency.
- FPGA Development
- Target high-end FPGAs (Xilinx Versal, Intel Agilex); perform synthesis, P&R, timing closure, and resource optimization.
- Integrate PCIe IP cores, DMA engines, and custom protocol decoders.
- Verification & Debug
- Build SystemVerilog/UVM testbenches for block and system-level verification.
- Conduct simulation, waveform analysis, and functional coverage to ensure robust design.
- System Integration
- Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms.
- Support lab debug using logic analyzers, oscilloscopes, and in-system FPGA tools (ILA/SignalTap).
- Documentation & Process
- Create design specifications, interface documents, and verification plans.
- Participate in design/code reviews and contribute to continuous improvement of design practices.
Required Qualifications
- BS in EE, CS or Computer Engineering required
- MS in EE is a plus
- 7 years of experience in digital logic design for FPGA or ASIC.
- Strong proficiency in Verilog/SystemVerilog RTL design.
- Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA
- Experience with Monitoring and/or Test & Measurement tools
- Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts.
- Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure.
- Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator).
- Solid understanding of CDC, clock domain design, and reset strategies.
Preferred Qualifications
- Experience with protocol analyzers, packet capture, and timestamping logic.
- Familiarity with AXI interconnects, memory controllers, and high-speed buffering.
- Exposure to SERDES, PCIe IP integration, and link training/debug.
- Scripting experience (Python, Tcl) for automation and test infrastructure.
- Experience with hardware/software co-design, register maps, and embedded firmware interaction.
- Prior work in test & measurement or semiconductor validation environments.
Work Environment
- Location: Milpitas, CA
- Travel: Minimal (<10%) for lab collaboration or customer support
- Team Culture: Collaborative, fast-paced, and innovation-driven