FPGA Designer

LOA: 3 Months

On site 3 days a week on site

From the manager- If they are proficient in RTL and Timing constraints, that can help.

Job Title: FPGA Engineer

Locations: Denver CO

Role Summary:

In this role, you ll be tasked with assessing and improving Xilinx-based FPGA emulation of our ASIC. You will review the current FPGA build environment, design constraints, and build/timing/utilization reports, and identify improvements and work with Design team to implement improvements to enable complete, accurate, functional, and stable builds on FPGA hardware.

What You ll Be Doing:

• Review current FPGA build environment, design constraints and implementation, and build/timing/utilization reports
• Update design constraints (XDC) to match ASIC design constraints (SDC). Clock frequency scaling as needed to appease FPGA limitations
• Identify FPGA build environment improvements
• Ensure FPGA design is following industry-standard best practices (clock and reset generation, Bidi buffer usage, etc)
• Assess viability of current FPGA hardware for the targeted RTL design
• Ensure FPGA can build, meet timing, and pass on-board testing
• Collaborate with RTL Design team, document work, and attend reoccurring status update meetings
• Use Git version control software daily

You ll Need These Qualifications:

• Master s or Bachelor s degree in Electrical Engineering, or similar field
• Experience with setting up, constraining, optimizing and closing timing on high utilization designs.
• Experience with Xilinx and Vivado

Desired Qualifications:

• Experience with Git version control software
• Experience with Jira project workflow software