Demo

Application-Specific Integrated Circuit Designer

Technical-Link N. America
Irvine, CA Contractor
POSTED ON 7/29/2026
AVAILABLE BEFORE 8/27/2026

Example Contractor Job Description

Title: Senior SRAM/DRAM RTL ASIC Design Engineer

Location: San Jose, CA / Irvine, CA / Austin, TX (hybrid depending on team)

Responsibilities

  • Design and implement RTL for memory subsystems in advanced ASIC products
  • Develop SRAM/DRAM controllers, arbitration logic, ECC, and performance optimization features
  • Collaborate with architecture, verification, and physical design teams
  • Drive RTL quality through simulation, lint, CDC, synthesis, and timing closure

Required Skills

  • 7 years ASIC RTL design experience
  • Expert SystemVerilog coding skills
  • Experience with SRAM/DRAM controllers
  • Strong understanding of ASIC design flow
  • Experience with UVM-based verification environments
  • Strong scripting skills (Python/Tcl/Perl)

Preferred

  • DDR5/HBM experience
  • AI accelerator or networking ASIC background
  • Advanced-node experience (5nm/4nm/3nm)


Salary : $90 - $100

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