What are the responsibilities and job description for the Design for Test position at Tara Technical Solutions (TTS)?
2 New Full-Time Principal and also a Senior DFT Openings.
Direct hire with our Fortune 500 Client.
San Jose.
*No Remote or Hybrid options.
Staff Or Sr.Staff Or Principal DFT-
Designs DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement
to meet the product test metrics.
It involves working with the Physical Design & STA team for DFT mode timing
closure.
Skills/Experience:
Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan,
BIST, and others)
Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
Experience in Verilog coding, testbench generation & simulation
Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM).
Boundary scan Verification and test vector generation.
Should have good knowledge in IEEE1149.1 and IEEE1149.6.
Basic knowledge Test-STA and constraints.
Strong background on IEE1687, IJTAG, ICL and PDL
The ability to work in a multi-disciplined, cross-department environment
Good understanding of Si processing, logical and physical synthesis, and transistor r
eliability principles.
Experience working on the ATE is a plus.
Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus.