What are the responsibilities and job description for the Application Specific Integrated Circuit Verification Engineer position at Tara Technical Solutions (TTS)?
New ASIC Verification Openings.
Artificial Intelligence/DataCenter and advanced LLM and memory acceleration.
Principal Leads and Sr.Staff and Staff Levels are all available.
H1B Transfer assistance is available.
Full-Time Direct Hire.
Early Stage Start-Up.
As part of the Verification team, you will be responsible for verification of silicon, IP and subsystems.
Provide technical leadership in defining IP/SOC verification from microarchitecture to design to tapeout.
Assist and partner teams across architecture, design, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum of 5 PLUS years of ASIC/SOC verification.
Excellent leadership, communication and stakeholder management skills.
Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
Outstanding technical expertise in verification methodologies.
Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
Optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
Verification and tapeout of any advanced silicon device is highly preferred.
Post-Silicon validation of any silicon ASIC/SoC is highly preferred.
Preferred Qualifications:
PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience managing relationships with external design partners, IP vendors, and foundries.
Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.