Analog IC Layout Design Engineer

Analog IC Layout Design Engineer

Richardson, TX (Hybrid – Tuesday through Thursday onsite)

About the Opportunity

We are partnering with an established and growing semiconductor engineering organization seeking an experienced Analog IC Layout Design Engineer to join its team in Richardson, TX.

This is an exciting opportunity to work on advanced semiconductor technologies, supporting complex analog, RF, and mixed-signal integrated circuit designs for a long-standing, high-profile customer.

The ideal candidate will have strong hands-on experience in full-custom IC layout, advanced FinFET technologies, and Cadence Virtuoso, with the ability to independently manage challenging layout assignments from development through verification.

This organization offers a collaborative engineering environment, flexible work schedules, long-term project stability, and opportunities for technical advancement and leadership.

Key Responsibilities

• Perform full-custom layout and physical verification of complex analog, RF, and mixed-signal integrated circuits.
• Develop layouts for critical circuit blocks, including PLLs, SerDes, ADCs, DACs, and RF components.
• Work with advanced FinFET and GAA semiconductor technologies, including 7nm, 4nm, and 3nm process nodes.
• Utilize Cadence Virtuoso/VXL and Calibre for layout development and physical verification, including DRC, LVS, and ERC.
• Apply advanced layout techniques involving device matching, shielding, guard rings, and latch-up prevention.
• Address layout-dependent effects such as electromigration, IR drop, RC delay, self-heating, and crosstalk.
• Develop hierarchical layouts using Design for Manufacturability (DFM) principles.
• Collaborate with design engineers and technical teams to optimize circuit performance, area, power, and reliability.
• Support verification activities from individual circuit blocks through top-level integration.
• Identify opportunities to improve design methodologies, layout quality, and engineering workflows.

Required Qualifications

• 3 years of hands-on experience in full-custom analog, RF, or mixed-signal IC layout. Exceptional candidates with less experience may be considered.
• Strong proficiency with Cadence Virtuoso/VXL and Calibre (DRC, LVS, ERC).
• Experience with advanced TSMC or Samsung FinFET/GAA process technologies, particularly 7nm, 4nm, or 3nm nodes.
• Experience laying out complex analog or mixed-signal blocks such as PLLs, SerDes, ADCs, and DACs.
• Strong understanding of analog layout fundamentals, including matching, shielding, guard rings, and latch-up.
• Knowledge of electromigration, IR drop, parasitic effects, crosstalk, and other layout-dependent considerations.
• Experience with hierarchical layout construction and DFM methodologies.
• Strong analytical, debugging, and communication skills.
• Bachelor's degree in Electrical Engineering or a related field. Candidates with an associate degree or technical training and significant custom mask layout experience will also be considered.
• Must be a U.S. citizen or lawful permanent resident to meet applicable export-control requirements.

Preferred Qualifications

• Experience with PERL or Cadence SKILL scripting.
• Ability to independently manage complex custom layout assignments.
• Previous experience supporting advanced semiconductor development programs.
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Compensation & Benefits

• Competitive hourly compensation of $43–$60/hour, depending on experience.
• Overtime opportunities
• Hybrid work schedule: onsite Tuesday through Thursday, remote Monday and Friday.
• Flexible working hours with core collaboration hours from 10 AM to 2 PM.
• Medical, dental, and vision benefits, with employee coverage beginning on day one.
• 401(k) retirement plan with company matching provisions.
• Life insurance and additional benefits.
• Opportunities for advancement into Senior Engineer, Technical Lead, and Engineering Management positions.