What are the responsibilities and job description for the Front-End ASIC Digital Design, Sr. Staff Engineer -18423 position at Synopsys Inc?
About The Role
We are seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off. You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design.
What You'll Be Doing:
We are seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off. You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design.
What You'll Be Doing:
- Drive front-end sign-off: static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design.
- Translate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems.
- Own timing constraint (SDC) development and review; support full-chip timing closure.
- Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.
- Apply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior.
- Run power estimation and analysis (PrimePower) and feed findings back into RTL optimization.
- Contribute to methodology improvement, scripting, and regression automation.
- BS/MS in Electrical/Computer Engineering or a related field, with 8 years of experience in ASIC design and STA sign-off.
- Demonstrated experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.
- Strong proficiency in SystemVerilog/Verilog RTL coding for synthesis.
- Solid understanding of synthesis (Design Compiler / Fusion Compiler) and QoR analysis.
- Experience with low-power design techniques: clock gating, power gating, multi-Vt, UPF.
- Working knowledge of SDC constraint development and timing closure methodology.
- Proficiency in scripting: TCL, Python, Perl, and Linux/UNIX environments.
- Command of digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB).
- High-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI).
- The quality of your RTL and sign-off discipline will shape how well our designs meet their performance, power, and area goals.
- Clean front-end sign-off from you means fewer late-stage surprises, fewer ECO cycles, and a predictable path to tape-out.
- The methodology and automation you build will raise the quality bar for every future project the team takes on.
- Your work ships in HPC and AI accelerator silicon deployed at scale in data centers worldwide.
- Curious and improvement-minded: You identify an inefficient workflow, which you then automate and turn it into a reusable capability for everyone.
- Accountable and proactive: You are hands-on and take the lead and responsibility for driving issues to a closure.
- A clear communicator: Your specifications, review feedback, and sign-off documentation provide clear guidance for stakeholders.
- Highly detail-oriented: You follow quality and sign-off checklists rigorously and prioritize finding issues early in the process than at a later stage.