Sr. Digital Engineer, ASIC

Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions. We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Overview

Synaptics is looking for a Sr. Digital Engineer on the Interface Products team. This role is a unique opportunity to participate in all aspects of digital design and implementation from specification to tapeout and debug in Synaptics’ next generation data and video connectivity ASICs. As a member of the digital design team, you will be responsible for architecture, RTL design, debug, implementation, test, and product support for block and full-chip designs. This position reports to the Sr. Manager, Digital Design Engineering.

The typical base pay range for this position is USD $100,000 - $157,300 per year. Individual pay is determined by many factors including work location, job-related skills, experience, and relevant education or training. This position is also eligible for a discretionary annual performance bonus, equity, and other benefits. Note that compensation listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities & Competencies

Job Duties

• Implement technical specifications, logic designs, verification, synthesis, DFT insertions, and integration of circuits in the next generation of Synaptics’ family of high-speed serial interface devices
• Develop RTL for module and chip-level designs in Verilog hardware design language, tcl/make/python scripts, and proprietary hardware specification languages
• Analyze designs and integrate them into the Synaptics ASIC & FPGA development environments by writing scripts, using proprietary tools, and using other vendor-supplied CAD tools
• Implement and integrate Memory BIST, Logic Scan, and custom ATE and debug test logic: partner with the verification team to write test plans and debug simulations
• Participate in silicon debug and analysis
• Complete designs on time that meet all specifications
  
  

Competencies

• Comprehensive understanding of IC digital design with the ability to assess unusual circumstances, reacting using analytical problem-solving skills to achieve technical goals
• Excellent debugging skills for hardware and/or software
• Proactive, self-starter, able to work independently in a fast-paced environment
• Well organized with strong attention to detail; proactively ensures work is accurate
• Positive attitude and work ethic; unafraid to ask questions and explore new ideas
• Resourceful and able to solve complex problems through practical use of technology and a solid understanding of product architecture
• Good verbal and written communication skills, in English
• Strong team player with the ability to work collaboratively within a diverse cross-functional team
  
  

Qualifications (Requirements)

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or related field or equivalent
• 5 years of IC digital design experience
• Experience writing synthesizable Verilog for ASIC & FPGA design
• Experience with ASIC/FPGA design flow and tools (DC, PT, PrimePower, Formality, Tetramax) is desirable
• No travel required
  
  

Belief in Diversity

Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.