Demo

Lead RTL Engineer

SWITS DIGITAL Private Limited
Austin, TX Contractor
POSTED ON 6/10/2026
AVAILABLE BEFORE 12/5/2026
Location: Austin, TX (Onsite)

Key Skills

  • RTL Lead experience
  • Processor/CPU Design
  • Microarchitecture and Architecture Ownership

Responsibilities

  • Translate architecture specifications into synthesizable SystemVerilog.
  • Own RTL coding standards, linting rules, and design methodology.
  • Lead a team of 5 to 7 RTL engineers through the full design cycle.
  • Own the synthesis flow using Design Compiler or Genus and drive timing closure.
  • Define and maintain SDC timing constraints.
  • Review all RTL code submissions for correctness, synthesizability, and coding standards.
  • Coordinate with outsourcing partners on GDSII handover, including netlists, constraints, and floorplan guidance.
  • Work closely with the verification team to resolve bugs and achieve coverage closure.

Requirements

  • 7 years of RTL design experience using SystemVerilog.
  • At least one tapeout experience through GDSII with full design flow exposure.
  • Hands-on experience with synthesis and timing closure using Design Compiler or Genus, and PrimeTime or Tempus.
  • Strong experience in Processor, DSP, or datapath-intensive designs.
  • Familiarity with advanced process nodes, 28nm or below.
  • Strong code review skills with the ability to identify timing hazards, FSM issues, and non-synthesizable coding patterns.
  • Experience leading a small team while remaining hands-on.
  • Excellent debugging and problem-solving skills.

Good to Have

  • VLIW or Vector Processor design experience.
  • Experience with deterministic or real-time architectures with fixed latencies and no caches.
  • Formal verification knowledge, including SVA and formal verification tools.
  • FPGA prototyping experience using Vivado.

Soft Skills

  • Strong systems thinking and ability to navigate large, complex FPGA architectures.
  • Exceptional problem-solving skills under tight timing and resource constraints.
  • Ability to collaborate effectively with hardware, embedded software, DSP, and systems engineering teams.
  • Excellent communication, documentation, and presentation skills.
  • Ability to make and defend architectural decisions under ambiguity and project pressure.

Hourly Wage Estimation for Lead RTL Engineer in Austin, TX
$62.00 to $75.00
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