Mixed Signal Model Verification Engineer

Mixed Signal Model Verification Engineer
Hybrid Role in San Jose, CA
3 Months

MUST HAVE SKILLS:
Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling
Strong understanding of HDL/SPICE co-simulations
Strong understanding of custom circuit schematic
Strong background in analog integrated circuit design
Proficiency in RTL design languages like SystemVerilog
Experience with formal equivalence checking tools like ESP

We are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number. It will involve writing constraints and stimulus for CAD tools to run equivalence check against the schematic. It is required to read and understand the mixed signal circuit schematic to debug any mismatch between behavioral model and circuit transistor-level behavior. Modification to the behavioral models to make it equivalent to the mixed signal circuit is expected.