ASIC Physical Design Engineer

he Mission

StaffRight Associates is recruiting to identify a high-caliber ASIC Physical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (SoC) architectures. This role is not merely about execution; it is about the technical synthesis of complex silicon requirements into high-performance, tape-out-ready reality. You will bridge the gap between front-end architectural intent and physical silicon constraints, driving custom ASIC solutions that power emerging technologies. Within this high-stakes environment, you will own the end-to-end physical lifecycle, transforming abstract logic into optimized, high-performance hardware.

Core Technical Objectives

• Formalize and validate pre-layout timing constraints to ensure architectural feasibility and systemic synchronization from the earliest stages of development.

• Architect block-level and chip-level floorplans, optimizing pin assignments and spatial distribution to maximize silicon efficiency and signal integrity.

• Orchestrate clock tree synthesis and complex clock specification reviews to ensure robust distribution across sophisticated SoC environments.

• Optimize placement and routing protocols through iterative timing analysis, ensuring high-density integration without compromising performance.

• Validate system resilience via rigorous sign-off procedures, including RC extraction, static timing analysis (STA), and IR-drop mitigation.

• Engineer solutions for complex physical verification (PV) discrepancies, utilizing advanced debugging methodologies to ensure zero-defect tape-outs.

• Synthesize technical findings into high-level presentations for strategic stakeholders, aligning engineering execution with client mission requirements.

Candidate DNA

• Technical Depth: A minimum of 8–10 years of hands-on mastery in custom ASIC physical design, with a proven history of navigating the full project lifecycle from inception to final tape-out.

• Domain Expertise: Expert-level command of advanced process nodes (e.g., 28nm, 16nm, and below) and deep familiarity with hierarchical layout strategies.

• Toolchain Proficiency: Advanced fluency in industry-standard physical design suites (ICC2/Innovus) and sign-off environments (PrimeTime, Redhawk, or equivalent IR-drop and STA platforms).

• Computational Logic: Skilled in automating complex workflows and design-rule checks through precise scripting in Tcl, Perl, or Python.

• Academic Foundation: Bachelor of Science in Electrical Engineering (BSEE) required; Master of Science (MSEE) preferred, with a focus on integrated circuit design or semiconductor physics.

• Professional Pedigree: Ideally experienced within lean, high-impact engineering environments where independent ownership and "Goal-Execution-Mapping" are essential for project success.

Working with StaffRight Associates

At StaffRight Associates, we operate at the intersection of technical synthesis and structural alignment. We don’t just match resumes to keywords; we map your engineering DNA—your architectural philosophy, your approach to system resilience, and your "Goal-Execution-Mapping"—to the most sophisticated STEM challenges in the industry. When you partner with us, you are engaging with a team that speaks your language and understands the nuances of high-stakes innovation. We are committed to placing elite talent where their technical contributions drive systemic impact.