Silicon Design Package Engineer

Position: Silicon Design Package Designer 

Location: Santa Clara, CA (Onsite)

This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies.

Key Responsibilities & Skills:

• Tools & Knowledge:
• Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
• Technical Expertise:
• Multi-layer package design experience.
• Understanding of substrate manufacturing Design Rules and Assembly Rules.
• Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
• Flip-chip package design concepts.

Tasks:

• Perform point-to-point connections.
• Run DRC (Design Rule Checks), identify root causes, and fix issues.
• Execute design based on provided schematics, including component placement and constraint setup.