What are the responsibilities and job description for the Senior Analog Layout Engineer (High-Speed SerDes) position at Spanidea Inc?
Job Title: Senior Analog Layout Engineer (High-Speed SerDes)
Location: San Jose, CA
Responsibilities
- Develop custom analog and mixed-signal layouts for high-speed SerDes designs using Cadence Virtuoso.
- Optimize layouts for performance, area, matching, and manufacturability while minimizing parasitics.
- Perform physical verification, including LVS/DRC signoff, and resolve layout-related issues.
- Support chip-level layout activities, including bump planning, pad-ring implementation, and ESD integration.
- Collaborate closely with circuit designers and cross-functional teams throughout the design cycle.
- Review foundry design rules and maintain layout documentation.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 5 years of IC layout experience, or 8 years of equivalent industry experience.
- Strong experience in custom analog and high-speed SerDes IC layout.
- Hands-on experience with Cadence Virtuoso, Calibre LVS/DRC, and Linux environments.
- Solid understanding of physical verification, foundry design rules, and advanced layout techniques.
- Excellent analytical, problem-solving, and communication skills.