Logic Design Engineer

Company Description

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

Job Description

Join Solidigm’s visionary Design Engineering Team as a 3D NAND Logic Design Engineer and help shape the future of memory technology.

Job responsibilities include, but not limited to:

• Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
• Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
• Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
• Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
• Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
• Support post-silicon debug and failure analysis across multiple configurations

Qualifications

• MS in electrical or computer engineering with 5 years of experience, or BS with 7 years of experience
• Hands‑on experience with micro‑controller architecture, instruction sets, and compilers, with the ability to design, implement, and debug micro‑code for memory control algorithms (read, program, erase, initialization, power‑on sequences)
• Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO
• Strong background in design verification tools and automation scripting
• Prior experience in 3D NAND Flash Memory logic design is a plus
• Ability to work independently across pre- and post-silicon debug cycles

Additional Information

The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

This is a Hybrid role reporting out of Rancho Cordova CA; or San Jose CA.