What are the responsibilities and job description for the Senior IC Package Design Engineer [Onste] position at SmartIPlace?
Position: Senior IC Package Design EngineerLocation: Santa Clara, CA (Onsite)Duration: 6 Months (Ongoing)Visa: Any (Onsite work required) RequirementsBachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Job ResponsibilitiesExperience with 2.5D package design and development like CoWoSStrong expertise in using IC package layout tools like Cadence APDUnderstanding IC package design requirements for high-speed interfaces and setup constraints managerInterface with the IC physical design teams for optimizing the die floor planExperience in interfacing with Substrate suppliers and OSATsAbility to do automation of the layout tasks using scriptingPower plane design and translating power supply requirements into designFamiliarity with IC packaging technologies, materials, substrate design rules and assembly rulesTrack record of new product introduction from concept through development and production is a plusKnowledge of the thermal and mechanical analysis of the IC package development is a plusA team player with strong communication, presentation, and documentation skills