What are the responsibilities and job description for the Sr Physical Design Engineer position at Sivaltech?
Job Title: Senior Physical Design (PD) Engineer
Company: Sivaltech Pvt. Ltd.
Location: Bay Area, California, USA (Onsite)
Experience: 8 Years
Job Description
Sivaltech Pvt. Ltd. is hiring an experienced Senior Physical Design (PD) Engineer to join our growing semiconductor team in the Bay Area, California. The ideal candidate should have strong expertise in end-to-end physical design implementation for advanced technology nodes.
Responsibilities
Perform complete Physical Design flow from netlist to GDSII.
Handle floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Optimize design for timing, power, area, and signal integrity.
Perform IR drop, EM, and power integrity analysis.
Work closely with RTL, DFT, STA, and verification teams.
Resolve DRC/LVS issues and support design sign-off.
Deliver high-quality designs within project timelines.
Required Skills
8 years of experience in Physical Design.
Strong hands-on experience with Cadence Innovus and/or Synopsys ICC2.
Expertise in floorplanning, placement, CTS, routing, STA, and physical verification.
Good understanding of SI, PI, IR drop, and EM analysis.
Experience with advanced technology nodes (16nm/7nm/5nm or below) is preferred.
Excellent debugging, communication, and teamwork skills.
Location
📍 Bay Area, California, USA (Onsite)
Apply Now
📧 Sridevi@sivaltech.com
#Hiring #PhysicalDesign #PDEngineer #VLSI #SemiconductorJobs #BayArea #California #OnsiteJobs #Sivaltech
Company: Sivaltech Pvt. Ltd.
Location: Bay Area, California, USA (Onsite)
Experience: 8 Years
Job Description
Sivaltech Pvt. Ltd. is hiring an experienced Senior Physical Design (PD) Engineer to join our growing semiconductor team in the Bay Area, California. The ideal candidate should have strong expertise in end-to-end physical design implementation for advanced technology nodes.
Responsibilities
Perform complete Physical Design flow from netlist to GDSII.
Handle floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Optimize design for timing, power, area, and signal integrity.
Perform IR drop, EM, and power integrity analysis.
Work closely with RTL, DFT, STA, and verification teams.
Resolve DRC/LVS issues and support design sign-off.
Deliver high-quality designs within project timelines.
Required Skills
8 years of experience in Physical Design.
Strong hands-on experience with Cadence Innovus and/or Synopsys ICC2.
Expertise in floorplanning, placement, CTS, routing, STA, and physical verification.
Good understanding of SI, PI, IR drop, and EM analysis.
Experience with advanced technology nodes (16nm/7nm/5nm or below) is preferred.
Excellent debugging, communication, and teamwork skills.
Location
📍 Bay Area, California, USA (Onsite)
Apply Now
📧 Sridevi@sivaltech.com
#Hiring #PhysicalDesign #PDEngineer #VLSI #SemiconductorJobs #BayArea #California #OnsiteJobs #Sivaltech