What are the responsibilities and job description for the MTS, DDR Design Verification (AI2487) position at SiMa.ai?
Description
Job Title: MTS, DDR Design Verification
Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)
Job ID: AI2487
Job Description
As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai’s MLSoC™. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab.
Required Background
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
The annual salary for this position ranges from $176,200 to $281,900. The actual annual salary paid for this position will be based on several factors, including but not limited to skills, prior experience, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands.
EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Job Title: MTS, DDR Design Verification
Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)
Job ID: AI2487
Job Description
As the DDR Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai’s MLSoC™. You will be responsible for developing DDR test plans, test-benches (drivers, monitors and checkers/scoreboard etc..) and test cases. You will be executing test plans to verify the MLSoC - DDR functionality, performance and coverage analysis. You will work closely with the Architecture, RTL/uArch, and cross-functional teams. Opportunity to participate on DDR bring up on MLSoC Silicon in the lab.
Required Background
- BS in Computer Science/EE with 10 years of experience or MS in computer science/EE with 8 years of experience in SoC design verification.
- Experience with block level, cluster level or chip/SoC level verification.
- Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
- DDR controller and/or DDR-IO verification experience is a must.
- Very good understanding of LPDDR JDEC specifications preferably for LPDDR5.
- Good understanding of DDR controller and phy functionality.
- Experience with development of test bench components, test plans for DDR/LPDDR IP verification.
- Good system verilog programming, debug and problem solving skills.
- Scripting languages, python or perl is a plus.
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
The annual salary for this position ranges from $176,200 to $281,900. The actual annual salary paid for this position will be based on several factors, including but not limited to skills, prior experience, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands.
EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Salary : $176,200 - $281,900