What are the responsibilities and job description for the Design Verification Engineer - Full Time / Permanent - AMBA/UVM / System Verilog - Sunnyvale CA or Austin TX position at Silverlink Technologies LLC?
We are looking for a Design Verification Engineer to join our team. Please review the job description below, and let us know if you are interested and available.
If this opportunity matches your experience and career goals, we would love to discuss it more. Additionally, feel free to share your updated resume for consideration
Role: Design Verification Engineer
Location: Sunnyvale CA or Austin TX
Salary Range: $130K - $170K
Full Time Role
Job Details:
Key Responsibilities:
Strong understanding of SV and UVM and good debugging skills.
Understanding of AMBA protocols.
Understand design specs and develop test plans based on functional and architectural requirements
Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
Debug simulation failures and work closely with RTL designers to resolve issues
Execute regression runs, analyze results, and contribute to continuous improvements
Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
Document test environments, testplans, and results for internal and external reviews
Time Zone
CA or TX location
Expected to be in Office 3 days a week (M-F)
Thank you!
Best Regards,
Sumit Talekar
Associate Manager – Talent Acquisition
Silverlink Technologies Inc.
Salary : $130,000 - $170,000