SoC Design Engineer

We are seeking a Senior SoC RTL Design Engineer to lead chip-top RTL design and integration, ensuring seamless subsystem, IP, and hard macro integration. The role includes RTL implementation, synthesis, I/O padring design, power/thermal analysis, and collaboration with Physical Design teams to drive timing closure and system-level optimization.

The ideal candidate has expertise in SoC architecture, RTL design, synthesis, and timing, with experience across DFT, Physical Design, Power/IR analysis, and Package Integration, and will partner closely with the Senior DFT Engineer for robust SoC-level DFT integration.

Responsibilities:

• Lead chip-top RTL design and integration across subsystems, IPs, and hard macros.
• Design and implement the SoC padring and integrate PLLs, PMUs, SRAMs, and PHYs.
• Define/validate timing and synthesis constraints; drive timing closure with robust CDC/RDC strategies.
• Collaborate with PD teams on floorplanning, power distribution, thermal limits, and IR drop optimization.
• Ensure SoC-level ESD protection, power domain partitioning, and package integrity (noise, crosstalk, EMI).
• Partner with DFT teams on scan, BIST, and JTAG integration; support post-silicon validation and debug.

Qualifications:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• At least 8 years of experience in SoC RTL design, integration, and implementation.
• Strong proficiency in SystemVerilog/HDL for complex SoC designs.
• Proven track record in chip-level integration of IPs, hard macros, and mixed-signal interfaces.
• Deep expertise in clocking architectures, CDC, and RDC methodologies.
• Hands-on experience with timing constraints (SDC), static timing analysis (STA), and timing closure.
• Proficiency with industry-standard EDA tools like Synopsys Design Compiler, Cadence Genus (or equivalent), PrimeTime, Tempus (or equivalent) Floorplanning and power/thermal analysis.
• Strong understanding of PDN design, IR drop, power integrity, and package-level constraints.
• Familiarity with DFT methodologies such as scan, BIST, and ATPG.
• Excellent problem-solving skills with the ability to work effectively across cross-functional teams.