Demo

Senior Engineer, Defect Engineering

Samsung Electronics America
Austin, TX Full Time
POSTED ON 6/15/2026
AVAILABLE BEFORE 7/15/2026
About Samsung Austin Semiconductor
Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At SAS, we are Innovating Today to Power the Devices of Tomorrow.

Come innovate with us!

Position Summary

As a Defect Reduction Engineer, the candidate will support defect control and reduction work in a high volume 24x7 manufacturing environment, on purpose to achieve yield and performance goals. Supporting New Product Introduction (NPI) as the Defect Reduction representative: attending meetings, presenting inline inspection strategy & methodology, supporting GPM set up, spec audits, and comparison, evaluating unit part process changes and tool spreads in terms of inline and NPW defectivity data. Performing fab process/tool trend data and correlation analysis to identify dog tools, trace defects to root cause, and rapidly take action to prevent inline process excursions. Working cross-functionally with YE/PIE/UP to evaluate defect data on BKMs & projects, excursion monitoring & control, SWLY reduction. Establishing FCC (Failed Chip Count) and trend monitoring plans for new technology introductions and ramps (14nm & foundry) and existing legacy production nodes (45nm/32nm/28nm) in order to achieve yield and performance goals, and support on weekly module meetings & activities. Responding to foundry customer requests and delivering the data & analysis to meet expectation. Supporting new technology and process transfer projects from Samsung HQ (South Korea).

Role and Responsibilities

Here's what you'll be responsible for:
  • Supporting New Product Introduction (NPI) as the Defect Reduction representative: attending meetings, presenting inline inspection strategy & methodology, supporting GPM set up, spec audits, and comparison, evaluating unit part process changes and tool spreads in terms of inline and NPW defectivity data.
  • Performing fab process/tool trend data and correlation analysis to identify dog tools, trace defects to root cause, and rapidly take action to prevent inline process excursions.
  • Working cross-functionally with YE/PIE/UP to evaluate defect data on BKMs & projects, excursion monitoring & control, SWLY reduction.
  • Establishing FCC (Failed Chip Count) and trend monitoring plans for new technology introductions and ramps (14nm & foundry) and existing legacy production nodes (45nm/32nm/28nm) in order to achieve yield and performance goals, and support on weekly module meetings & activities.
  • Responding to foundry customer requests and delivering the data & analysis to meet expectation.
  • Supporting new technology and process transfer projects from Samsung HQ (South Korea).

Skills and Qualifications

Here's what you'll need:
  • Requires a Bachelor's degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics or related technical fields. Requires a minimum of 10 years of Semiconductor process engineering experience in defect monitor and reduction.
  • Experience in leading logic technology (45nm or below) development is strongly preferred.
  • Relevant experience in advanced defect inspection and review tools (bright field, dark field, e-beam, Vis-edge...etc) is strongly preferred.
  • Knowledge of Klarity Defect (or similar) software and its application in a semiconductor processing environment is useful.
  • Working knowledge in SPC and DOE methodology is required
  • Excellent communication skills (written, verbal and presentation) and experience as a contributing member of cross functional teams is required
  • Strong data mining, troubleshooting skills and an energetic self-starter personality preferred.
  • Strong organizational skills to manage multiple tasks and able to react to shifting priorities. Ability to meet deadlines, schedules and commitments is required.

Total Rewards
At Samsung SAS, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.

We offer a comprehensive benefits package, including:
  • Medical, dental, and vision insurance
  • Life insurance and 401(k) matching with immediate vesting
  • Onsite caf(s) and workout facilities
  • Paid maternity and paternity leave
  • Paid time off (PTO) 2 personal holidays and 10 regular holidays
  • Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

All positions at SAS are full-time on-site.

U.S. Export Control Compliance
This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Trade Secrets Notice
By submitting an application, you agree not to disclose to Samsung-or encourage Samsung to use-any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Salary.com Estimation for Senior Engineer, Defect Engineering in Austin, TX
$123,640 to $143,584
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