What are the responsibilities and job description for the DV Engineer position at RIIM?
Strong System Verilog/UVM knowledge with practical experience on live projects
Expertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable)
Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding tools
Experience in developing functional verification environments, including components like monitors, checkers, scoreboards, and assertions, along with knowledge of verification methodologies using random stimulus and functional coverage.
Hourly Wage Estimation for DV Engineer in Dallas, TX
$42.00 to $49.00
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