What are the responsibilities and job description for the Senior PDK Development Engineer position at Rapidus Corporation US?
About Rapidus
Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.
Why Join Us
You will play a central leadership role in building the world’s most advanced 2nm and next‑generation enablement ecosystem, shaping the foundation for future semiconductor innovation.
You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)
The Enablement team at Rapidus is responsible for delivering high-quality Process Design Kits (PDKs) that enable designers to create innovative IC products on our advanced technology nodes. Within the team, the PDK group is focused on developing, maintaining, and supporting the full suite of PDK components including design rules, layout verification, parasitic extraction, and QA automation.
As a Senior PDK Development Engineer, you will play a key role in ensuring the completeness, accuracy, and usability of PDKs provided to both internal and external customers. This includes development of rule decks for industry-standard EDA tools, coordination with technology development, and continuous quality improvement.
Work Location
As indicated in the posting, the primary workplace for this role is expected to in Albany, New York, but we are also considering the possibility of hiring in Japan (Tokyo) for this role, based on candidate profiles.
Key Responsibilities
- Develop, maintain, and improve PDK components such as DRC, LVS, and RC extraction rule decks.
- Build and enhance PDK QA flows and validation methodologies.
- Create and maintain PDK documentation for internal and external users.
- Provide PDK-related support to both internal design teams and external customers.
- Collaborate with EDA vendors, IP providers, and the process development team to align PDK deliverables with technology updates and customer needs.
Required Qualifications
- Master’s degree in Electrical Engineering or related STEM field.
- 10 years of experience in semiconductor design enablement or PDK development.
- Deep understanding of the full design-to-tapeout workflow, including schematic, simulation, layout, physical verification, RC extraction, and mask generation.
- 7 years of experience with:
- DRC runset development (e.g., Siemens Calibre, Cadence Pegasus, Synopsys ICV)
- LVS runset development for advanced technology nodes
- Parasitic extraction (PEX) rule deck development (e.g., StarRC, Quantus, xACT)
Benefits
Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles), 401k with no employer match.