Microarchitecture Lead / RTL

JOB DESCRIPTION

Job Title: Microarchitecture Lead

Experience: 12 Years

Role Overview

We are seeking a Microarchitecture Lead to define and deliver next-generation Custom HBM4e Base Die silicon enabling AI/HPC platforms. This role owns micro-architecture, RTL execution, and silicon success for ultra-high bandwidth memory subsystems implemented on advanced nodes and integrated via 2.5D/3D packaging.

You will operate at the intersection of memory architecture, high-speed interfaces, power integrity, and advanced packaging — driving system-level PPA for multi-TB/s class memory stacks.

Key Responsibilities

• Own micro-architecture and RTL implementation of HBM4e base die subsystems including memory controller, DFI/PHY interfaces, clocking, and power architecture
• Architect and optimize ultra-high bandwidth (>6.4 GT/s per pin class) memory datapaths for latency, throughput, and efficiency
• Drive integration of ARM-based system components where applicable (debug, control processors, AMBA-based infrastructure)
• Define system debug and bring-up strategy including CoreSight-class infrastructure and performance monitoring
• Lead UVM-based verification and co-simulation with ARM CPU models where required
• Drive synthesis, timing constraints, lint, CDC closure, and PPA optimization at advanced nodes (N3P/N2P or equivalent)
• Partner with SI/PI, package, and thermal teams for 2.5D/3D integration (interposer, TSV, hybrid bonding)
• Support silicon bring-up, characterization, and post-silicon performance tuning

Required Experience

• 12 years in ASIC/SoC micro-architecture and RTL design
• Strong expertise in Verilog/SystemVerilog, synthesis, STA, and timing closure
• Deep familiarity with AMBA protocols and SoC debug infrastructure
• Proven experience with high-speed memory interfaces (HBM2E/3/3E; HBM4 preferred)
• Strong understanding of signal integrity, power integrity, and high-density memory design constraints
• Experience across full silicon lifecycle through bring-up

Preferred

• Experience with 2.5D/3D packaging and chiplet-based integration
• Exposure to CXL, PCIe Gen6, or coherency protocols
• Experience with DRAM controllers and memory PHY integration
• Prior AI accelerator or data center-class silicon experience

Pay Range : $160,000 - $240,000