What are the responsibilities and job description for the Lead Verification Engineer position at Quest Global?
Quest Global is seeking talent for Lead Verification Engineer role. Please review below job description :
Title :: Lead Verification Engineer
Location :: Sunnyvale, CA
- Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Develop tests using UVM or C/C
- Analyze and debug test failures with designers to deliver functionally correct design.
Qualifications
- 10 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
- Knowledge of verification principles, testbenches, stimulus generation, and UVM or C based test environments.
- Good understanding of computer architecture
- Scripting language such as Python or Perl