What are the responsibilities and job description for the Principal Digital IC Design Engineer position at Qorvo, Inc.?
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.
We are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow ASIC development lifecycle, driving projects from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up.
The ideal candidate possesses deep expertise across both front-end design and back-end implementation, serving as a strategic authority who bridges the gap between hardware architecture, microarchitecture, and complex physical layout constraints.
Key Responsibilities
Technical Leadership & Strategy
Education & Experience
We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.
We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.
We are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow ASIC development lifecycle, driving projects from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up.
The ideal candidate possesses deep expertise across both front-end design and back-end implementation, serving as a strategic authority who bridges the gap between hardware architecture, microarchitecture, and complex physical layout constraints.
Key Responsibilities
Technical Leadership & Strategy
- Define, establish, and optimize cutting-edge ASIC design methodologies and full-flow architectures across the organization.
- Act as the chief technical authority to align cross-functional domains including Architecture, RTL Design, Verification, and Physical Design.
- Provide expert guidance on complex engineering trade-offs evaluating Power, Performance, and Area (PPA).
- Translate complex system-level product requirements into functional SoC/ASIC microarchitectures.
- Write high-quality, scalable, and synthesizable hardware description code using SystemVerilog/Verilog.
- Collaborate closely with Design Verification (DV) teams to review test plans and implement advanced Design for Testability (DFT) structures
- Drive full chip-level and block-level execution through synthesis, floorplanning, and automated Place & Route (P&R) flows.
- Formulate and sign off on rigorous Timing Constraints and execute deep Static Timing Analysis (STA) to resolve setup/hold violations.
- Oversee structural physical verification including DRC, LVS, and ERC checks to guarantee tape-out readiness.
Education & Experience
- Bachelor’s degree in Electrical Engineering
- 12 years of expereince or equivalent amount of advanced education and experience in direct, practical industry experience in digital ASIC design and implementation with a proven history of multiple successful commercial tape-outs.
- Hardware Languages: Mastery of SystemVerilog and Verilog.
- Full-Flow Implementation: Comprehensive hands-on command of the RTL-to-GDSII flow (Logic Synthesis, Floorplanning, CTS, P&R, STA, and Physical Verification).
- EDA Tool Ecosystems: Deep proficiency with flagship EDA toolsuites from Synopsys (Design Compiler, IC Compiler II, PrimeTime) or Cadence (Genus, Innovus, Tempus).
- Scripting & Automation: Strong programming proficiency in Python, TCL, and Bash/Perl for methodology customization and CAD data manipulation.
- Post-Silicon Execution: Direct experience with actual silicon bring-up, hardware debugging, and lab evaluation.
- Strong mentorship capabilities with a track record of leveling up senior and mid-level engineering talent.
- Excellent written and verbal communication skills, with the ability to articulate highly abstract hardware complexities to non-technical stakeholders
- Master’s or PhD degree in Electrical Engineering
- Prior experience with Power Management IC’s
We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.
We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.