What are the responsibilities and job description for the DFT Engineer (Scan / MBIST / ATPG) position at Programmers.io?
Job Description:
Position: DFT Engineer (Scan / MBIST / ATPG)
Location: Mountain View CA (On-site)
Hire Type: Full Time / Contract
We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs.
Key Responsibilities:
• Develop and implement Design-for-Test (DFT) architecture for IPs and SoCs.
• Perform Scan insertion and Scan chain verification.
• Integrate and validate MBIST solutions for embedded memories.
• Generate ATPG patterns for stuck-at, transition, and other manufacturing fault models.
• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.
• Analyze and improve fault coverage while reducing pattern count.
• Debug DFT-related issues during implementation and verification.
• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.
• Support silicon bring-up and production test activities when required.
Required Skills:
• Strong understanding of DFT fundamentals.
• Hands-on experience in:
o Scan Architecture
o Scan Insertion
o Scan Compression
o MBIST Integration
o ATPG Pattern Generation
o ATPG Simulation
o Fault Coverage Analysis
o DFT Verification
• Experience with industry-standard DFT tools such as:
o Tessent
o Synopsys DFT Compiler
o TetraMAX / TestMAX ATPG
o Modus (preferred)
• Good knowledge of Verilog/SystemVerilog and simulation environments.
• Familiarity with manufacturing test concepts and silicon debug.
Preferred Qualifications:
• Experience with large SoC or CPU/GPU designs.
• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.
• Experience supporting post-silicon test and yield improvement activities