What are the responsibilities and job description for the Senior ASIC Design Engineer position at Persimmons, Inc.?
Who we are:
Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.
Why join us:
We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.
What you'll do:
As a Persimmons Senior ASIC Design Engineer, you will be responsible for building and verifying the Persimmons Chiplet that will run the smallest to largest AI models. Your primary duties and responsibilities include:
What You Bring To The Table:
Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.
Why join us:
We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.
What you'll do:
As a Persimmons Senior ASIC Design Engineer, you will be responsible for building and verifying the Persimmons Chiplet that will run the smallest to largest AI models. Your primary duties and responsibilities include:
- Design High Performance Compute & High Speed Data Transport logic optimized for AI inference workloads
- Collaborate to integrate 3rd party & open source IP
- Partner with DV engineers to develop comprehensive verification strategies, drive coverage closure, and debug complex cross-functional issues
- Develop automation and methodologies to improve productivity and quality
- Create detailed technical documentation including microarchitecture specifications, integration guides, and design reviews
- Contribute to architectural decisions that balance performance, power, area & schedule
- Collaborate with Physical Design teams to ensure RTL quality supports timing closure, power targets, and manufacturability on advanced process nodes
What You Bring To The Table:
- BS/MS in Electrical Engineering, Computer Engineering, or related field
- 5 years of hands-on ASIC design experience with complex digital logic in SystemVerilog
- Proven record of designing high performance compute & high speed data transport logic
- Experience integrating fabric & high-speed IO like PCIe/HBM/etc
- Proficiency with testbench creation, simulation environments and synthesis flows
- Experience with scripting languages such as Python, Perl, or TCL for automation
- Self-motivated & able to thrive in fast-paced, ambiguous start-up environments
- Ability to learn about AI inference & passionate about building next-generation AI silicon
- Competitive salary and benefits package
- Flexible PTO
- 401k
