What are the responsibilities and job description for the System Architect - Memory Solutions position at Penguin Solutions?
System Architect, Memory Solutions
Overview
We are seeking a visionary and technically exceptional Senior System Architect to lead the design and development of a next-generation optical-based memory appliance. This role is pivotal in shaping high-performance computing infrastructure for AI/ML workloads, leveraging silicon photonics, HBM and DDR5 memory, and ultra-high-speed communication links capable of terabits per second.
As a Senior Member of Technical Staff (MTS), you will architect scalable, low-latency memory systems optimized for large-scale training and inference applications. You’ll collaborate across hardware, firmware, and software teams to push the boundaries of memory bandwidth, energy efficiency, and compute density.
What We Offer
The base pay range that the Company reasonably expects to pay for this position is $160,000-190,000; the pay ultimately offered may vary based on business considerations, including job-related knowledge, skills, experience, and education. The position is bonus-eligible, and there are medical, dental, and vision benefits available. There is a 401k saving plan and other benefits, such as Paid Time Off, Life Insurance, and an Employee Assistance Plan.
Inclusion & Belonging Statement
We are committed to creating an inclusive environment that embraces differences and fosters belonging for all.
Equal Opportunity Statement
We are an Affirmative Action/Equal Opportunity Employer and strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.
Overview
We are seeking a visionary and technically exceptional Senior System Architect to lead the design and development of a next-generation optical-based memory appliance. This role is pivotal in shaping high-performance computing infrastructure for AI/ML workloads, leveraging silicon photonics, HBM and DDR5 memory, and ultra-high-speed communication links capable of terabits per second.
As a Senior Member of Technical Staff (MTS), you will architect scalable, low-latency memory systems optimized for large-scale training and inference applications. You’ll collaborate across hardware, firmware, and software teams to push the boundaries of memory bandwidth, energy efficiency, and compute density.
What We Offer
- Opportunity to shape the future of AI infrastructure
- Work with world-class engineers in a fast-paced, innovation-driven environment
- Competitive compensation and benefits
- Flexible work arrangements and career development support
- Lead system architecture design for an optical memory appliance integrating:
- Silicon photonics-based interconnects
- High Bandwidth Memory (HBM) and DDR5 memory subsystems
- Tbps-class communication and routing (e.g., PCIe Gen5/6, CXL, custom optical fabrics)
- Define and drive system-level requirements, performance targets, and integration strategies for AI/ML workloads
- Collaborate with photonics, packaging, and signal integrity teams to optimize physical layer design
- Evaluate trade-offs in latency, bandwidth, power, and scalability across memory and interconnect technologies
- Guide hardware/software co-design for memory management, data movement, and inference acceleration
- Author architecture specifications, design documents, and technical roadmaps
- Mentor junior engineers and contribute to technical leadership across the organization
- Bachelor’s degree in Computer Science, Electrical Engineering, or related field (Master’s preferred)
- 10 years of experience in system architecture or hardware design for high-performance computing, memory systems, or networking
- Deep expertise in data center and edge server systems, memory hierarchy design, silicon photonics, and high-speed interconnects
- Proven track record architecting systems for AI/ML training or inference at scale
- Strong understanding of HBM, DDR5, CXL, PCIe, and optical signaling technologies
- Experience with simulation, modeling, and performance analysis tools
- Excellent communication and cross-functional collaboration skills
- Ability to identify key patentable ideas and work with patent attorneys on filing disclosures and patents a strong plus
- Familiarity with photonic IC design and packaging
- Experience with accelerator architectures (GPU, TPU, custom ASICs)
- Knowledge of AI/ML frameworks and memory access patterns
- Contributions to industry standards or academic publications in relevant domains
- Remote, Newark CA or Irvine CA
- Travel to US industry conferences, major customers or partners expected to be around 1-2 times per month.
- Potential international travel depending on partner and/or customer engagement levels.
The base pay range that the Company reasonably expects to pay for this position is $160,000-190,000; the pay ultimately offered may vary based on business considerations, including job-related knowledge, skills, experience, and education. The position is bonus-eligible, and there are medical, dental, and vision benefits available. There is a 401k saving plan and other benefits, such as Paid Time Off, Life Insurance, and an Employee Assistance Plan.
Inclusion & Belonging Statement
We are committed to creating an inclusive environment that embraces differences and fosters belonging for all.
Equal Opportunity Statement
We are an Affirmative Action/Equal Opportunity Employer and strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.
Salary : $160,000 - $190,000