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Senior Firmware Engineer

OSI Engineering
Palo Alto, CA Contractor
POSTED ON 6/21/2026
AVAILABLE BEFORE 9/6/2026

Senior Firmware Engineer


Company Overview

Company is developing a next-generation AI wearable that combines ultra-high-density neural sensing with a Brain Foundation Model to decode neural signals and convert thought into text without surgery. The company is focused on advancing noninvasive brain-computer interface (BCI) technology, enabling real-time interaction between the human brain and AI. Their goal is to create a direct connection between mind and machine through an EEG-powered wearable platform designed for communication, productivity, and human augmentation.


Position Summary

Generalist with rotating focus across the firmware stack. Moves across subsystems as work demands, picks up a primary domain at a time (RTOS and low-power state machines, wireless connectivity, sensor-acquisition drivers, inter-MCU bridges) and rotates as priorities shift. Works under the Lead FW's architectural direction. Works extensively with external engineering teams at CMs and silicon vendors, the work is outsourced; the accountability is shared with the Lead.


Responsibilities:

  • Own subsystem-level firmware under the Lead FW's architectural direction.
  • Take an assigned subsystem from spec through driver implementation, integration, bring-up, and validation.
  • Rotate across primary domains as the roadmap demands.
  • Run hands-on bring-up and debug — first power-on, peripheral bring-up, bus traffic validation, timing analysis, deep-sleep budget verification — with JTAG/SWD, logic analyzers, and protocol sniffers.
  • Partner with EE lead and EE ICs on co-debug for new boards — own the firmware side of bring-up checklists.
  • Partner with audio, camera, and biosensor leads to integrate their algorithms into the firmware runtime.
  • Contribute to the team's firmware engineering practices.
  • Drive external silicon-vendor engagement.


Requirements:

  • 5 years embedded firmware — at least one shipped consumer product where you owned a subsystem end-to-end.
  • Hands-on Zephyr RTOS experience on Nordic silicon (nRF5x, nRF53, or nRF54L families) — peripheral drivers, deep-sleep state machines, low-power optimization, interrupt-driven design.
  • Hands-on ESP-IDF firmware experience on ESP32-family silicon — Wi-Fi/BLE stack integration, multi-radio coexistence, OTA infrastructure.
  • Hands-on STM32 firmware experience — HAL/LL drivers, CubeMX toolchain, timer/DMA/peripheral configuration.
  • Hands-on experience writing sensor-acquisition drivers on standard buses (SPI, I²C, I²S, USB) — DMA-driven sampling, ring buffers, hardware-aligned timestamping.
  • Comfortable in the lab — JTAG/SWD, logic analyzers, protocol sniffers.
  • Direct experience partnering with EE on hardware bring-up and co-debug.
  • Experience with Nordic Semiconductor nRF52 family devices.
  • Experience with SoC bring-up.
  • Experience with sensor hub development and integration.
  • Experience with PPG sensor integration is preferred.
  • Ability to work across multiple areas of embedded systems development.
  • Generalist mindset with flexibility to support changing project priorities.


Desired Skillsets:

  • Raspberry Pi or comparable Linux SBC firmware experience — userspace drivers, bus interaction with attached MCUs, Linux-side tooling for development-host bring-up.
  • Adjacent embedded ecosystems — FreeRTOS, ThreadX, NuttX, or bare-metal Cortex-M development.
  • ARM secure-partition development (TrustZone or comparable).
  • On-device flash file system work — LittleFS, SPIFFS, or equivalent on SPI NAND/NOR.
  • Hosting real-time DSP runtimes alongside wireless connectivity on resource-constrained MCUs.
  • Hardware-aligned cross-sensor timestamping for biopotential signal chains.
  • Early-stage or contract experience at a consumer hardware startup.
  • Experience with Wi-Fi and Bluetooth Low Energy (BLE) is preferred.
  • Experience with DSP/DSD-related development is a plus.
  • Familiarity with relevant signal chains is a nice-to-have.


Location: Palo Alto, CA (Hybrid Schedule, 2 days/week in office)

Duration: 12-month contract with extension/conversion possibilities

Pay Rate Range: $75 to $95

Salary : $75 - $95

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