What are the responsibilities and job description for the Principle Hardware Design Engineer - Systems Engineering position at Oraapps Inc?
Location: Santa Clara, CA (100% On-site)
Position Type: Full-Time, Permanent
Benefits: Industry-leading Corporate Package (ESPP with 2-year lookback, Mental Health & Family Support)
Equity: Premium RSU Package (Standard 4-year vesting schedule)
Domain/Industry:
Position Overview:
A premier global innovator in semiconductor architecture and cloud infrastructure solutions is seeking a senior-level Principle Hardware Design Engineer to join their core Systems Engineering team in Santa Clara, CA.
This critical on-site role focuses on developing and designing cutting-edge reference boards for chip validation, working in close synchronization with enterprise, cloud, and AI network architectures. The successful candidate will drive high-speed PCB layouts, execute complex power integrity simulations, and maintain oversight across next-generation validation pipelines.
Key Responsibilities:
Reference Board Design: Lead the full lifecycle development and schematic capture of advanced reference boards specifically built for enterprise chip validation and AI compute systems.
High-Speed Architecture: Execute comprehensive engineering designs utilizing high-speed differential pairs, PCIe Gen4/Gen5 protocols, and complex PAM-4 signaling environments.
Power & Mechanical Engineering: Architect low-voltage, high-current, multi-phase SMPS (Switch Mode Power Supply) controllers and perform deep power integrity (PI) analysis across layouts.
Simulation & Tooling: Leverage advanced electronic design automation (EDA) and simulation software, including Sigrity, SI Soft, HFSS, and Cadence Concept, to ensure signal integrity.
Component Optimization: Manage absolute component selection, oversee high-frequency clock generation and distribution networks, and integrate structural mechanical design concepts into the PCB lifecycle.
Minimum Requirements (Strict Must-Haves):
Experience Level: Senior to Principal level professional background with a proven track record in high-speed hardware design and system-level engineering.
Technical Stack: Direct hands-on expertise with PCIe Gen4/Gen5, PAM-4 signaling, multi-phase SMPS design, and signal/power integrity simulation tools.
Tool Proficiency: Mastery of Cadence Concept, HFSS, Sigrity, or SI Soft for layout modeling and design validation.
Compliance & Legal: Must be fully eligible to access export-controlled technical information as strictly defined by U.S. export control laws, including the Export Administration Regulations (EAR).
Salary : $150,000 - $220,000