Digital Design Engineer

• Define block-level design specifications, including interface protocols, block diagrams, transaction flows, and pipeline architecture.
• Participate in chip-level architecture definition, focusing on ALS datapath design and performing power, performance, and area (PPA) trade-off analysis using Spyglass.
• Complete RTL coding of functional blocks in alignment with full-chip integration timelines.
• Perform RTL design and coding using Verilog/SystemVerilog.
• Conduct functional and performance simulation debugging.
• Execute Lint, CDC (Clock Domain Crossing), UPF (Unified Power Format), and formal verification (FV) checks to ensure design quality and robustness.
• Develop and contribute to test plans and perform coverage analysis at both block and SoC levels.
• Implement and verify analog sensor timing behavior models using SystemVerilog.
• Conduct timing control design and verification for image sensor arrays and analog-related circuits using Verilog and Python.
• Perform schematic and behavioral logic equivalence checks using Cadence Virtuoso.
• Perform full-chip integration and verification using industry-standard tools such as SimVision and Verdi.
• Collaborate with the back-end team to support floor planning, DFT (Design-for-Test), and timing closure.
• Synthesis, Timing & Power Optimization
• Participate in logic synthesis and assist in achieving timing and power closure across design blocks.
• Perform FPGA prototyping, chip bring-up, and system-level validation.
• Debug silicon using a combination of FPGA platforms and Python-based test environments.

• Hardware RTL low power design and optimization;
• Scalable mesh network design;
• Complex stage pipeline and SIMD design;
• Floating-point and non-linear operation hardware design;
• Optimizing SRAM usage efficiency of neural networks;
• Kernel fusion, event-based processing and data prefetch hardware design;
• Research and development of hardware friendly neural network lossless weight compression algorithm;
• OS coding techniques, IP protocols, interfaces and hardware subsystems;
• Programming and debugging in C and Python;
• Logic analyzer and debugging embedded systems;
• Reading schematics and data sheets for software driver development on the SoC;
• Knowledge with neural network algorithms and architectures;
• Knowledge with code management tools such as svn, git, repo.

Salary : $125,000 - $138,000