Demo

Design For Test (DFT) Engineer Intern - Summer 2026

NXP Semiconductors
Chandler, AZ Intern
POSTED ON 4/24/2026
AVAILABLE BEFORE 5/23/2026
In this position, the selected candidate will have a strong learning opportunity on state of the art mixed-signal design for test flow, and improve the efficiency using strong automation skills.

The Responsibilities Will Include

  • Study the existing DfT workflow.
  • Identify and develop automation to expedite impactful parts of the workflow
  • Deliver end to end efficiency in workstream using AI-assisted automation.

Candidate Should Have

  • Solid communication and problem-solving skills.
  • Excellent scripting proficiency in Python.
  • Basic knowledge of AI agents and agentic AI
  • Knowledge of system Verilog is a plus
  • Currently pursuing a BS or MS degree in Electrical Engineering, Computer Engineering, or similar

In order to be considered for an internship with NXP, you must be returning to school (or graduating) at the conclusion of the internship term. If you are graduating before August 2026, please only apply for Entry Level or other full-time roles.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

Hourly Wage Estimation for Design For Test (DFT) Engineer Intern - Summer 2026 in Chandler, AZ
$36.00 to $42.00
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