"Technical Detective" (Opto-MEMS Failure Analysis Engineer)

nEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability.

In bringing this MEMS silicon-photonics optical switch to life at scale, understandably things break, drift, warp, delaminate, outgas, arc, and fail in exquisitely interesting ways. We need a hands-on investigator who lives to answer “why?”, then turns answers into fixes. Think technical Sherlock Holmes: part physicist, part FA engineer, part builder who can move between wafer, die, package, module, and rack-level systems and close the loop from symptom to root cause and then corrective action -- a true Technical Detective.

• Triage & reproduce elusive failures across devices, subassemblies, and full systems (electro-optical, mechanical, thermal, firmware-interaction symptoms).
• Frame the hypothesis space: turn vague symptoms into crisp, ranked hypotheses; design scrappy experiments and minimum test rigs to kill the wrong ones fast.
• Interrogate parts & materials: plan and execute FA with internal tools and external labs (SEM/FIB/EDX, SAM, X-ray/CT, optical microscopy/interferometry, profilometry, ellipsometry, SIMS, FTIR, TGA/DSC, leak/outgas).
• Instrument & measure: optical (insertion loss, PDL/PMD, spectra), electrical (IV/CV, noise, leakage), mechanical (resonance, stiction, friction, creep), thermal (hot-spots, gradients), and time-domain behavior.
• Reliability sleuthing (not a “career REL” role): plan targeted stress screens (temp-cycle, THB, HTOL, HALT/HASS, vibration/shock), derive Weibull/Arrhenius models where useful, lead and maintain cross-functional FMEAs (DFMEA/PFMEA) to identify failure modes early and ensure that design and process mitigations are traceable and verified; link failure physics to design/process fixes.
• Root-cause to corrective action: use 5-Whys, Ishikawa, 8D, DOE/JMP, SPC to get to physics-based RCAs; drive containment permanent fix with design, process, packaging, and test owners.
• Build the toolbox: decide when to buy a tool, hack a fixture, or use an external lab; qualify vendors; create FA playbooks and lab SOPs.
• Communicate like a pro: write tight, visual reports and give exec-level readouts that separate cause, correlation, and conjecture; keep dashboards current.
• Close the loop: verify fixes via experiment, characterize margins, and lock in updated control plans and incoming/outgoing tests with Foundry/Test/OPS.

• BS/MS/PhD in Physics, Applied Physics, Materials Science, or similar (EE/ME with strong failure-physics chops also works).
• Hands-on lab athlete: comfort tearing down, probing, wiring, aligning optics, scripting quick analyses, and building fixtures.
• Demonstrated track record of root-causing multi-disciplinary hardware problems (optical/electrical/mechanical/thermal interactions).
• Practical familiarity with a meaningful subset of: SEM/FIB/EDX, interferometry, SAM/X-ray, leak/outgas, IV/CV, high-speed logging, DOE/JMP, SPC.
• Reliability literacy: can design fit-for-purpose stress tests and interpret Weibull/Arrhenius without making REL your identity.
• Clear, concise communicator: can brief technicians at 9am and execs at 5pm with the same facts, tuned to audience.
• Startup mindset: bias to action, frugal creativity, and joy in ambiguity.

• Experience in MEMS, silicon photonics, opto-MEMS, precision packaging, or micro-assembly.
• Prior work with foundry/OSAT partners and external FA labs; basic vendor qualification savvy.
• Data wrangling: Python/MATLAB for quick analyses, instrument control, and plots; familiarity with JMP/Spotfire.
• Light firmware or test automation (PyVISA, LabVIEW) to stand up repeatable experiments.
• Knowledge of cleanroom processes (litho/etch/depo/CMP/wafer bonding) and how they manifest as field failures.
• System-level debug in racks/servers (signal integrity, power/thermal interactions).

nEye is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. 

Salary : $160,000 - $220,000