What are the responsibilities and job description for the Lead FPGA Design Engineer position at Neurophos?
About Neurophos
The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of computing!
Position Overview
We are seeking an experienced and adaptable FPGA Development Lead to join our foundational silicon team. In this capacity, you will serve as the architect of our hardware emulation and validation strategy, bridging RTL design and physical silicon. As an early team member at a rapidly evolving ASIC startup, your responsibilities will extend beyond coding to encompass the entire FPGA lifecycle, including selecting appropriate hardware platforms and executing complex system-level bring-up and post-silicon characterization.
Location: Austin, TX. Full-time onsite position.
Key Responsibilities
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Benefits
Join a team that invests in your future and your well-being. At Neurophos, we offer:
The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of computing!
Position Overview
We are seeking an experienced and adaptable FPGA Development Lead to join our foundational silicon team. In this capacity, you will serve as the architect of our hardware emulation and validation strategy, bridging RTL design and physical silicon. As an early team member at a rapidly evolving ASIC startup, your responsibilities will extend beyond coding to encompass the entire FPGA lifecycle, including selecting appropriate hardware platforms and executing complex system-level bring-up and post-silicon characterization.
Location: Austin, TX. Full-time onsite position.
Key Responsibilities
- Lead the selection and procurement of FPGA prototyping platforms (e.g., HAPS, VCU118, or custom boards) tailored for pre-silicon RTL verification and software development.
- Adapt and implement complex ASIC RTL onto FPGA targets using SystemVerilog.
- Integrate a mix of in-house designs and third-party IP. You will be the expert on Xilinx-specific IP (Vivado IP Integrator, Transceivers, Memory Controllers).
- Design and debug high-speed interfaces, with a specific focus on PCIe Gen 3/4/5 integration and validation.
- Develop FPGA-based "tester" designs to facilitate post-silicon validation, device characterization, and automated testing environments.
- Utilize ChipScope/Vivado Analyzer and external lab equipment (oscilloscopes, logic analyzers) to solve complex timing and functional issues in a real-time environment.
- 10 years of industry experience
- 5 years of experience in FPGA design and implementation, preferably within an ASIC or high-growth hardware environment.
- Expert-level proficiency in SystemVerilog for synthesis and verification.
- Deep experience with Xilinx Vivado (Synthesis, Place & Route, Timing Closure, and IP
- Catalog).
- Proven experience implementing and debugging PCIe interfaces, as well as SPI, UART, JTAG, and other common interfaces.
- Startup mindset: the ability to pivot quickly, work independently, and tackle ambiguous technical challenges.
- Strong hands-on experience with board-level bringup and lab debugging.
- Experience with scripting languages (Python or Tcl) for automation of FPGA builds and testing.
- Knowledge of SoC architectures and AMBA bus protocols (AXI, AHB).
- Familiarity with high-speed SERDES tuning and signal integrity concepts.
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Benefits
Join a team that invests in your future and your well-being. At Neurophos, we offer:
- 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
- Unlimited PTO. No rigid vacation banks, just a focus on delivery.
- 401(k) matching and stock option opportunities to ensure our success is your success.
- Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
- Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.