Test Engineer

THE PERSON:

We are looking for candidates that are strong DFT/ATPG engineers that can work on tight timelines, with a global team and be able to communicate effectively to cross-functioning technical teams. Strong DFT skills will be put to good use in a technically challenging environment.

JOB DUTIES: As a part of the DFT design team, successful candidates will be responsible for scan/ATPG testing of leading edge SoC, participating in chip level flow development, pattern retargeting and simulation, pattern generation and simulation, scan timing simulations, working with test engineering teams for successful silicon bring-up of scan patterns.

PREFERRED EXPERIENCE:

• Experience with Tessent Streaming Scan Network SSN and hand-on experience with retargeting flows.

• Experience in creating and implementing complex chip-level DFT flows

• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level

• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.

• Proficient in logic design using Verilog and experience in synthesis and STA

• Experience in simulation in RTL/GATE/SDF environments

• Good communication skills, works well in a group environment that spans across continents

• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc