[DRAFT] PCIe SSD Validation Engineer

1. Execute PCIe validation: Execute Gen4/Gen5/Gen6 link and protocol tests across different platforms and system configurations.Validate SSD behaviour under abnormal and corner conditions & provide periodic PCIe validation readouts for critical program milestones.
2. Collaborate: Triage failures from regression, bring‐up, and customer scenarios; correlate PCIe traces, NVMe/OCP logs, and system logs. Partner with FW, HW, and systems teams to root‐cause and verify fixes, and roll improvements back into the test suite.
3. PCIe tools: Leverage PCIe analyzers/exercisers for trace capture, error injection. Use oscilloscopes, logic analyzers, BERTs, and related tools (as needed) to support signal‐ and protocol‐level debug.
4. Test Roadmap & leadership: Lead coverage improvements based on lessons learned, standardize PCIe test APIs, logs, and reporting for reuse across products & share PCIe debug and test BKMs

Requirements:
6 years experience in SSD, storage, or PCIe‐centric validation / bring‐up (or equivalent embedded / high‐speed I/O domain).
Master's or Bachelor's Degree in Computer Engineering or Electrical Engieering
Comfortable with Python (or similar) for test and tooling development; able to work effectively in Linux‐based validation environments.
Experience with CI / regression infrastructure (e.g., Jenkins, Git‐based workflows) for large‐scale test execution.
Hands‐on experience using PCIe analyzers/exercisers (e.g., Teledyne/LeCroy, Keysight, or similar) for trace capture and debug is a plus
Strong debug skills across HW/FW/system boundaries is a plus
Clear written and verbal communication, with the ability to present findings, trade‐offs, and recommendations to engineering and program teams.
Highly self‐motivated, detail‐oriented, and comfortable operating in a fast‐paced development environment.