What are the responsibilities and job description for the Lead Architecture Modeling Engineer position at Mythic?
About Us
Mythic is pioneering next-generation compute-in-memory technology that’s redefining the future of AI. Our unique Mythic Dataflow Processing Unit (DPU)—powered by the Mythic Analog Compute Engine (Mythic ACE™) and a custom digital dataflow architecture—delivers 100–1000× greater efficiency than traditional all-digital systems, unlocking industry-leading performance per watt per dollar. Designed for flexible scalability, a single Mythic chip can power ultra-efficient edge devices, while multiple chips can be combined to tackle demanding datacenter-scale workloads such as state-of-the-art LLMs—all with best-in-class latency.
Architecture Modeling At Mythic
At Mythic, architecture modeling is at the core of how we design and deliver breakthrough AI hardware. Our models allow us to quantify the real-world performance of new architectures—capturing critical tradeoffs in throughput, latency, and efficiency—before a single chip is built.
Modeling plays a central role in active design development, predicting how AI workloads generated by the Mythic compiler will run on silicon. These models serve as a golden reference for verifying RTL implementations and enable our software teams to begin developing validation and customer-facing code long before hardware is available.
Even after silicon arrives, our modeling tools remain invaluable, offering deeper insight into performance bottlenecks and guiding ongoing software optimization.
Responsibilities
Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.
We look forward to reviewing your application!
Mythic is pioneering next-generation compute-in-memory technology that’s redefining the future of AI. Our unique Mythic Dataflow Processing Unit (DPU)—powered by the Mythic Analog Compute Engine (Mythic ACE™) and a custom digital dataflow architecture—delivers 100–1000× greater efficiency than traditional all-digital systems, unlocking industry-leading performance per watt per dollar. Designed for flexible scalability, a single Mythic chip can power ultra-efficient edge devices, while multiple chips can be combined to tackle demanding datacenter-scale workloads such as state-of-the-art LLMs—all with best-in-class latency.
Architecture Modeling At Mythic
At Mythic, architecture modeling is at the core of how we design and deliver breakthrough AI hardware. Our models allow us to quantify the real-world performance of new architectures—capturing critical tradeoffs in throughput, latency, and efficiency—before a single chip is built.
Modeling plays a central role in active design development, predicting how AI workloads generated by the Mythic compiler will run on silicon. These models serve as a golden reference for verifying RTL implementations and enable our software teams to begin developing validation and customer-facing code long before hardware is available.
Even after silicon arrives, our modeling tools remain invaluable, offering deeper insight into performance bottlenecks and guiding ongoing software optimization.
Responsibilities
- Technically leading and growing a team of at least 3-4 modeling engineers.
- Architect and create various types of hardware models with varying goals - e.g. transaction-level, cycle-accurate.
- Create or build on top of existing hardware models to simulate functionality of custom AI software.
- Create prototyping models for estimating power, performance and area of new chip architectures.
- Create cycle-accurate models of the hardware (C /SystemC).
- Collaborate with peer engineering teams to co-design and co-verify the hardware implementation.
- Investigate new architectural ideas, many co-designed with other system components.
- 5 years experience as a technical lead or technical manager.
- Bachelors / Masters / PhD degree in electrical/computer engineering or computer science.
- 10 years experience required creating performance models for architectural investigations. This experience can include time spent in academic work including papers, thesis, and dissertation work. The years required can be reduced if prior modeling experience is related to systems for AI.
- Academic and working knowledge of a variety of hardware concepts such as CPUs, memory systems, bus interconnects, security, chip interfaces, etc.
- Proficiency and experience with C /SystemC as used in modeling.
- Proficiency and experience with hardware modeling for performance and/or power.
- Strong communication skills, both written and spoken.
Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.
We look forward to reviewing your application!